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authorTim Newsome <tim@sifive.com>2017-06-14 14:13:53 -0700
committerTim Newsome <tim@sifive.com>2017-06-15 12:44:50 -0700
commitac2da40f745db385ecf2458f011dc122390821bc (patch)
tree6c597d71c9863c954db6845d01dbf4b41d820173
parent363a0a2bf2896794120ac8387f2058cd5f65c2c5 (diff)
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Fix indentation to match OpenOCD style.
This change is just in the whitespace. There are no code changes. See http://openocd.org/doc-release/doxygen/stylec.html
-rw-r--r--src/target/riscv/asm.h36
-rw-r--r--src/target/riscv/batch.c52
-rw-r--r--src/target/riscv/gdb_regs.h32
-rw-r--r--src/target/riscv/opcodes.h186
-rw-r--r--src/target/riscv/riscv-013.c286
-rw-r--r--src/target/riscv/riscv.c76
6 files changed, 333 insertions, 335 deletions
diff --git a/src/target/riscv/asm.h b/src/target/riscv/asm.h
index 051e0f9..67ac14f 100644
--- a/src/target/riscv/asm.h
+++ b/src/target/riscv/asm.h
@@ -6,31 +6,31 @@
/*** Version-independent functions that we don't want in the main address space. ***/
static uint32_t load(const struct target *target, unsigned int rd,
- unsigned int base, uint16_t offset) __attribute__ ((unused));
+ unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t load(const struct target *target, unsigned int rd,
- unsigned int base, uint16_t offset)
+ unsigned int base, uint16_t offset)
{
- switch (riscv_xlen(target)) {
- case 32:
- return lw(rd, base, offset);
- case 64:
- return ld(rd, base, offset);
- }
- assert(0);
+ switch (riscv_xlen(target)) {
+ case 32:
+ return lw(rd, base, offset);
+ case 64:
+ return ld(rd, base, offset);
+ }
+ assert(0);
}
static uint32_t store(const struct target *target, unsigned int src,
- unsigned int base, uint16_t offset) __attribute__ ((unused));
+ unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t store(const struct target *target, unsigned int src,
- unsigned int base, uint16_t offset)
+ unsigned int base, uint16_t offset)
{
- switch (riscv_xlen(target)) {
- case 32:
- return sw(src, base, offset);
- case 64:
- return sd(src, base, offset);
- }
- assert(0);
+ switch (riscv_xlen(target)) {
+ case 32:
+ return sw(src, base, offset);
+ case 64:
+ return sd(src, base, offset);
+ }
+ assert(0);
}
#endif
diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c
index d48b34a..5d680d5 100644
--- a/src/target/riscv/batch.c
+++ b/src/target/riscv/batch.c
@@ -123,34 +123,34 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
void dump_field(const struct scan_field *field)
{
- static const char *op_string[] = {"-", "r", "w", "?"};
- static const char *status_string[] = {"+", "?", "F", "b"};
+ static const char *op_string[] = {"-", "r", "w", "?"};
+ static const char *status_string[] = {"+", "?", "F", "b"};
- if (debug_level < LOG_LVL_DEBUG)
- return;
+ if (debug_level < LOG_LVL_DEBUG)
+ return;
assert(field->out_value != NULL);
- uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
- unsigned int out_op = get_field(out, DTM_DMI_OP);
- unsigned int out_data = get_field(out, DTM_DMI_DATA);
- unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
-
- if (field->in_value) {
- uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
- unsigned int in_op = get_field(in, DTM_DMI_OP);
- unsigned int in_data = get_field(in, DTM_DMI_DATA);
- unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
-
- log_printf_lf(LOG_LVL_DEBUG,
- __FILE__, __LINE__, __PRETTY_FUNCTION__,
- "%db %s %08x @%02x -> %s %08x @%02x [0x%p -> 0x%p]",
- field->num_bits,
- op_string[out_op], out_data, out_address,
- status_string[in_op], in_data, in_address,
+ uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
+ unsigned int out_op = get_field(out, DTM_DMI_OP);
+ unsigned int out_data = get_field(out, DTM_DMI_DATA);
+ unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
+
+ if (field->in_value) {
+ uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
+ unsigned int in_op = get_field(in, DTM_DMI_OP);
+ unsigned int in_data = get_field(in, DTM_DMI_DATA);
+ unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
+
+ log_printf_lf(LOG_LVL_DEBUG,
+ __FILE__, __LINE__, __PRETTY_FUNCTION__,
+ "%db %s %08x @%02x -> %s %08x @%02x [0x%p -> 0x%p]",
+ field->num_bits,
+ op_string[out_op], out_data, out_address,
+ status_string[in_op], in_data, in_address,
field->out_value, field->in_value);
- } else {
- log_printf_lf(LOG_LVL_DEBUG,
- __FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
- field->num_bits, op_string[out_op], out_data, out_address);
- }
+ } else {
+ log_printf_lf(LOG_LVL_DEBUG,
+ __FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",
+ field->num_bits, op_string[out_op], out_data, out_address);
+ }
}
diff --git a/src/target/riscv/gdb_regs.h b/src/target/riscv/gdb_regs.h
index e366f7d..e16fa7f 100644
--- a/src/target/riscv/gdb_regs.h
+++ b/src/target/riscv/gdb_regs.h
@@ -2,27 +2,27 @@
#define TARGET__RISCV__GDB_REGS_H
enum gdb_regno {
- GDB_REGNO_XPR0 = 0,
+ GDB_REGNO_XPR0 = 0,
GDB_REGNO_X0 = GDB_REGNO_XPR0 + 0,
GDB_REGNO_ZERO = GDB_REGNO_XPR0 + 0,
GDB_REGNO_S0 = GDB_REGNO_XPR0 + 8,
GDB_REGNO_S1 = GDB_REGNO_XPR0 + 9,
- GDB_REGNO_XPR31 = GDB_REGNO_XPR0 + 31,
- GDB_REGNO_PC = 32,
- GDB_REGNO_FPR0 = 33,
- GDB_REGNO_FPR31 = GDB_REGNO_FPR0 + 31,
- GDB_REGNO_CSR0 = 65,
- GDB_REGNO_TSELECT = CSR_TSELECT + GDB_REGNO_CSR0,
- GDB_REGNO_TDATA1 = CSR_TDATA1 + GDB_REGNO_CSR0,
- GDB_REGNO_TDATA2 = CSR_TDATA2 + GDB_REGNO_CSR0,
- GDB_REGNO_MISA = CSR_MISA + GDB_REGNO_CSR0,
- GDB_REGNO_DPC = CSR_DPC + GDB_REGNO_CSR0,
- GDB_REGNO_DCSR = CSR_DCSR + GDB_REGNO_CSR0,
+ GDB_REGNO_XPR31 = GDB_REGNO_XPR0 + 31,
+ GDB_REGNO_PC = 32,
+ GDB_REGNO_FPR0 = 33,
+ GDB_REGNO_FPR31 = GDB_REGNO_FPR0 + 31,
+ GDB_REGNO_CSR0 = 65,
+ GDB_REGNO_TSELECT = CSR_TSELECT + GDB_REGNO_CSR0,
+ GDB_REGNO_TDATA1 = CSR_TDATA1 + GDB_REGNO_CSR0,
+ GDB_REGNO_TDATA2 = CSR_TDATA2 + GDB_REGNO_CSR0,
+ GDB_REGNO_MISA = CSR_MISA + GDB_REGNO_CSR0,
+ GDB_REGNO_DPC = CSR_DPC + GDB_REGNO_CSR0,
+ GDB_REGNO_DCSR = CSR_DCSR + GDB_REGNO_CSR0,
GDB_REGNO_DSCRATCH = CSR_DSCRATCH + GDB_REGNO_CSR0,
- GDB_REGNO_MSTATUS = CSR_MSTATUS + GDB_REGNO_CSR0,
- GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
- GDB_REGNO_PRIV = 4161,
- GDB_REGNO_COUNT
+ GDB_REGNO_MSTATUS = CSR_MSTATUS + GDB_REGNO_CSR0,
+ GDB_REGNO_CSR4095 = GDB_REGNO_CSR0 + 4095,
+ GDB_REGNO_PRIV = 4161,
+ GDB_REGNO_COUNT
};
#endif
diff --git a/src/target/riscv/opcodes.h b/src/target/riscv/opcodes.h
index 3e1f8a2..c4d9baf 100644
--- a/src/target/riscv/opcodes.h
+++ b/src/target/riscv/opcodes.h
@@ -6,203 +6,203 @@
#define S1 9
static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
- return (value >> lo) & ((1 << (hi+1-lo)) - 1);
+ return (value >> lo) & ((1 << (hi+1-lo)) - 1);
}
static uint32_t bit(uint32_t value, unsigned int b) {
- return (value >> b) & 1;
+ return (value >> b) & 1;
}
static uint32_t jal(unsigned int rd, uint32_t imm) __attribute__ ((unused));
static uint32_t jal(unsigned int rd, uint32_t imm) {
- return (bit(imm, 20) << 31) |
- (bits(imm, 10, 1) << 21) |
- (bit(imm, 11) << 20) |
- (bits(imm, 19, 12) << 12) |
- (rd << 7) |
- MATCH_JAL;
+ return (bit(imm, 20) << 31) |
+ (bits(imm, 10, 1) << 21) |
+ (bit(imm, 11) << 20) |
+ (bits(imm, 19, 12) << 12) |
+ (rd << 7) |
+ MATCH_JAL;
}
static uint32_t csrsi(unsigned int csr, uint16_t imm) __attribute__ ((unused));
static uint32_t csrsi(unsigned int csr, uint16_t imm) {
- return (csr << 20) |
- (bits(imm, 4, 0) << 15) |
- MATCH_CSRRSI;
+ return (csr << 20) |
+ (bits(imm, 4, 0) << 15) |
+ MATCH_CSRRSI;
}
static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 5) << 25) |
- (src << 20) |
- (base << 15) |
- (bits(offset, 4, 0) << 7) |
- MATCH_SW;
+ return (bits(offset, 11, 5) << 25) |
+ (src << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_SW;
}
static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 5) << 25) |
- (src << 20) |
- (base << 15) |
- (bits(offset, 4, 0) << 7) |
- MATCH_SD;
+ return (bits(offset, 11, 5) << 25) |
+ (src << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_SD;
}
static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 5) << 25) |
- (src << 20) |
- (base << 15) |
- (bits(offset, 4, 0) << 7) |
- MATCH_SH;
+ return (bits(offset, 11, 5) << 25) |
+ (src << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_SH;
}
static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 5) << 25) |
- (src << 20) |
- (base << 15) |
- (bits(offset, 4, 0) << 7) |
- MATCH_SB;
+ return (bits(offset, 11, 5) << 25) |
+ (src << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_SB;
}
static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 0) << 20) |
- (base << 15) |
- (bits(rd, 4, 0) << 7) |
- MATCH_LD;
+ return (bits(offset, 11, 0) << 20) |
+ (base << 15) |
+ (bits(rd, 4, 0) << 7) |
+ MATCH_LD;
}
static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 0) << 20) |
- (base << 15) |
- (bits(rd, 4, 0) << 7) |
- MATCH_LW;
+ return (bits(offset, 11, 0) << 20) |
+ (base << 15) |
+ (bits(rd, 4, 0) << 7) |
+ MATCH_LW;
}
static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 0) << 20) |
- (base << 15) |
- (bits(rd, 4, 0) << 7) |
- MATCH_LH;
+ return (bits(offset, 11, 0) << 20) |
+ (base << 15) |
+ (bits(rd, 4, 0) << 7) |
+ MATCH_LH;
}
static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 0) << 20) |
- (base << 15) |
- (bits(rd, 4, 0) << 7) |
- MATCH_LB;
+ return (bits(offset, 11, 0) << 20) |
+ (base << 15) |
+ (bits(rd, 4, 0) << 7) |
+ MATCH_LB;
}
static uint32_t csrw(unsigned int source, unsigned int csr) __attribute__ ((unused));
static uint32_t csrw(unsigned int source, unsigned int csr) {
- return (csr << 20) | (source << 15) | MATCH_CSRRW;
+ return (csr << 20) | (source << 15) | MATCH_CSRRW;
}
static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused));
static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
{
- return (bits(imm, 11, 0) << 20) |
- (src << 15) |
- (dest << 7) |
- MATCH_ADDI;
+ return (bits(imm, 11, 0) << 20) |
+ (src << 15) |
+ (dest << 7) |
+ MATCH_ADDI;
}
static uint32_t csrr(unsigned int rd, unsigned int csr) __attribute__ ((unused));
static uint32_t csrr(unsigned int rd, unsigned int csr) {
- return (csr << 20) | (rd << 7) | MATCH_CSRRS;
+ return (csr << 20) | (rd << 7) | MATCH_CSRRS;
}
static uint32_t csrrs(unsigned int rd, unsigned int rs, unsigned int csr) __attribute__ ((unused));
static uint32_t csrrs(unsigned int rd, unsigned int rs, unsigned int csr) {
- return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRS;
+ return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRS;
}
static uint32_t csrrw(unsigned int rd, unsigned int rs, unsigned int csr) __attribute__ ((unused));
static uint32_t csrrw(unsigned int rd, unsigned int rs, unsigned int csr) {
- return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRW;
+ return (csr << 20) | (rs << 15) | (rd << 7) | MATCH_CSRRW;
}
static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 5) << 25) |
- (bits(src, 4, 0) << 20) |
- (base << 15) |
- (bits(offset, 4, 0) << 7) |
- MATCH_FSW;
+ return (bits(offset, 11, 5) << 25) |
+ (bits(src, 4, 0) << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_FSW;
}
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 5) << 25) |
- (bits(src, 4, 0) << 20) |
- (base << 15) |
- (bits(offset, 4, 0) << 7) |
- MATCH_FSD;
+ return (bits(offset, 11, 5) << 25) |
+ (bits(src, 4, 0) << 20) |
+ (base << 15) |
+ (bits(offset, 4, 0) << 7) |
+ MATCH_FSD;
}
static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t flw(unsigned int dest, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 0) << 20) |
- (base << 15) |
- (bits(dest, 4, 0) << 7) |
- MATCH_FLW;
+ return (bits(offset, 11, 0) << 20) |
+ (base << 15) |
+ (bits(dest, 4, 0) << 7) |
+ MATCH_FLW;
}
static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset) __attribute__ ((unused));
static uint32_t fld(unsigned int dest, unsigned int base, uint16_t offset)
{
- return (bits(offset, 11, 0) << 20) |
- (base << 15) |
- (bits(dest, 4, 0) << 7) |
- MATCH_FLD;
+ return (bits(offset, 11, 0) << 20) |
+ (base << 15) |
+ (bits(dest, 4, 0) << 7) |
+ MATCH_FLD;
}
static uint32_t fmv_x_s(unsigned dest, unsigned src) __attribute__ ((unused));
static uint32_t fmv_x_s(unsigned dest, unsigned src)
{
- return src << 15 |
- dest << 7 |
- MATCH_FMV_X_S;
+ return src << 15 |
+ dest << 7 |
+ MATCH_FMV_X_S;
}
static uint32_t fmv_x_d(unsigned dest, unsigned src) __attribute__ ((unused));
static uint32_t fmv_x_d(unsigned dest, unsigned src)
{
- return src << 15 |
- dest << 7 |
- MATCH_FMV_X_D;
+ return src << 15 |
+ dest << 7 |
+ MATCH_FMV_X_D;
}
static uint32_t fmv_s_x(unsigned dest, unsigned src) __attribute__ ((unused));
static uint32_t fmv_s_x(unsigned dest, unsigned src)
{
- return src << 15 |
- dest << 7 |
- MATCH_FMV_S_X;
+ return src << 15 |
+ dest << 7 |
+ MATCH_FMV_S_X;
}
static uint32_t fmv_d_x(unsigned dest, unsigned src) __attribute__ ((unused));
static uint32_t fmv_d_x(unsigned dest, unsigned src)
{
- return src << 15 |
- dest << 7 |
- MATCH_FMV_D_X;
+ return src << 15 |
+ dest << 7 |
+ MATCH_FMV_D_X;
}
static uint32_t ebreak(void) __attribute__ ((unused));
@@ -213,15 +213,15 @@ static uint32_t ebreak_c(void) { return MATCH_C_EBREAK; }
static uint32_t fence_i(void) __attribute__ ((unused));
static uint32_t fence_i(void)
{
- return MATCH_FENCE_I;
+ return MATCH_FENCE_I;
}
static uint32_t lui(unsigned int dest, uint32_t imm) __attribute__ ((unused));
static uint32_t lui(unsigned int dest, uint32_t imm)
{
- return (bits(imm, 19, 0) << 12) |
- (dest << 7) |
- MATCH_LUI;
+ return (bits(imm, 19, 0) << 12) |
+ (dest << 7) |
+ MATCH_LUI;
}
/*
@@ -267,10 +267,10 @@ static uint32_t nop(void)
static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm) __attribute__ ((unused));
static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
{
- return (bits(imm, 11, 0) << 20) |
- (src << 15) |
- (dest << 7) |
- MATCH_XORI;
+ return (bits(imm, 11, 0) << 20) |
+ (src << 15) |
+ (dest << 7) |
+ MATCH_XORI;
}
static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt) __attribute__ ((unused));
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 899c098..fa240df 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -201,17 +201,17 @@ static void dump_field(const struct scan_field *field)
unsigned int out_data = get_field(out, DTM_DMI_DATA);
unsigned int out_address = out >> DTM_DMI_ADDRESS_OFFSET;
- uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
- unsigned int in_op = get_field(in, DTM_DMI_OP);
- unsigned int in_data = get_field(in, DTM_DMI_DATA);
- unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
+ uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
+ unsigned int in_op = get_field(in, DTM_DMI_OP);
+ unsigned int in_data = get_field(in, DTM_DMI_DATA);
+ unsigned int in_address = in >> DTM_DMI_ADDRESS_OFFSET;
- log_printf_lf(LOG_LVL_DEBUG,
- __FILE__, __LINE__, "scan",
- "%db %s %08x @%02x -> %s %08x @%02x",
- field->num_bits,
- op_string[out_op], out_data, out_address,
- status_string[in_op], in_data, in_address);
+ log_printf_lf(LOG_LVL_DEBUG,
+ __FILE__, __LINE__, "scan",
+ "%db %s %08x @%02x -> %s %08x @%02x",
+ field->num_bits,
+ op_string[out_op], out_data, out_address,
+ status_string[in_op], in_data, in_address);
}
@@ -321,7 +321,7 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
struct scan_field field = {
.num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH,
.out_value = out,
- .in_value = in
+ .in_value = in
};
assert(info->abits != 0);
@@ -375,7 +375,7 @@ static uint64_t dmi_read(struct target *target, uint16_t address)
// it is actually due to the Previous dmi_read or dmi_write.
for (i = 0; i < 256; i++) {
status = dmi_scan(target, NULL, NULL, DMI_OP_READ, address, 0,
- false);
+ false);
if (status == DMI_STATUS_BUSY) {
increase_dmi_busy_delay(target);
} else if (status == DMI_STATUS_SUCCESS) {
@@ -423,39 +423,39 @@ static void dmi_write(struct target *target, uint16_t address, uint64_t value)
dmi_status_t status = DMI_STATUS_BUSY;
unsigned i = 0;
- // The first loop ensures that we successfully sent the write request.
- for (i = 0; i < 256; i++) {
- status = dmi_scan(target, NULL, NULL, DMI_OP_WRITE, address, value,
- address == DMI_COMMAND);
- if (status == DMI_STATUS_BUSY) {
- increase_dmi_busy_delay(target);
- } else if (status == DMI_STATUS_SUCCESS) {
- break;
- } else {
- LOG_ERROR("failed write to 0x%x, status=%d\n", address, status);
- break;
- }
- }
-
- if (status != DMI_STATUS_SUCCESS) {
- LOG_ERROR("Failed write to 0x%x;, status=%d\n",
- address, status);
- abort();
- }
-
- // The second loop isn't strictly necessary, but would ensure that
- // the write is complete/ has no non-busy errors before returning from this function.
- for (i = 0; i < 256; i++) {
- status = dmi_scan(target, NULL, NULL, DMI_OP_NOP, address, 0,
- false);
- if (status == DMI_STATUS_BUSY) {
- increase_dmi_busy_delay(target);
- } else if (status == DMI_STATUS_SUCCESS) {
- break;
- } else {
- LOG_ERROR("failed write (NOP) at 0x%x, status=%d\n", address, status);
- break;
- }
+ // The first loop ensures that we successfully sent the write request.
+ for (i = 0; i < 256; i++) {
+ status = dmi_scan(target, NULL, NULL, DMI_OP_WRITE, address, value,
+ address == DMI_COMMAND);
+ if (status == DMI_STATUS_BUSY) {
+ increase_dmi_busy_delay(target);
+ } else if (status == DMI_STATUS_SUCCESS) {
+ break;
+ } else {
+ LOG_ERROR("failed write to 0x%x, status=%d\n", address, status);
+ break;
+ }
+ }
+
+ if (status != DMI_STATUS_SUCCESS) {
+ LOG_ERROR("Failed write to 0x%x;, status=%d\n",
+ address, status);
+ abort();
+ }
+
+ // The second loop isn't strictly necessary, but would ensure that
+ // the write is complete/ has no non-busy errors before returning from this function.
+ for (i = 0; i < 256; i++) {
+ status = dmi_scan(target, NULL, NULL, DMI_OP_NOP, address, 0,
+ false);
+ if (status == DMI_STATUS_BUSY) {
+ increase_dmi_busy_delay(target);
+ } else if (status == DMI_STATUS_SUCCESS) {
+ break;
+ } else {
+ LOG_ERROR("failed write (NOP) at 0x%x, status=%d\n", address, status);
+ break;
+ }
}
if (status != DMI_STATUS_SUCCESS) {
LOG_ERROR("failed to write (NOP) 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
@@ -1101,10 +1101,10 @@ static int examine(struct target *target)
LOG_DEBUG("found program buffer at 0x%08lx", (long)(r->debug_buffer_addr[i]));
if (riscv_program_gah(&program64, r->debug_buffer_addr[i])) {
- LOG_ERROR("This implementation will not work with hart %d with debug_buffer_addr of 0x%lx\n", i,
- (long)r->debug_buffer_addr[i]);
+ LOG_ERROR("This implementation will not work with hart %d with debug_buffer_addr of 0x%lx\n", i,
+ (long)r->debug_buffer_addr[i]);
abort();
- }
+ }
/* Check to see if we can use the data words as an extended
* program buffer or not. */
@@ -1131,80 +1131,78 @@ static int examine(struct target *target)
/* Resumes all the harts, so the debugger can later pause them. */
riscv_resume_all_harts(target);
target_set_examined(target);
-
- // This print is used by some regression suites to know when
- // they can connect with gdb/telnet.
- // We will need to update those suites if we want to remove this line.
- LOG_INFO("Examined RISC-V core");
+
+ // This print is used by some regression suites to know when
+ // they can connect with gdb/telnet.
+ // We will need to update those suites if we want to remove this line.
+ LOG_INFO("Examined RISC-V core");
return ERROR_OK;
}
static int assert_reset(struct target *target)
{
- /*FIXME -- this only works for single-hart.*/
- RISCV_INFO(r);
- assert(r->current_hartid == 0);
+ /*FIXME -- this only works for single-hart.*/
+ RISCV_INFO(r);
+ assert(r->current_hartid == 0);
- select_dmi(target);
- LOG_DEBUG("ASSERTING NDRESET");
- uint32_t control = dmi_read(target, DMI_DMCONTROL);
- control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
- if (target->reset_halt) {
- LOG_DEBUG("TARGET RESET HALT SET, ensuring halt is set during reset.");
- control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
- } else {
- LOG_DEBUG("TARGET RESET HALT NOT SET");
- control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
- }
+ select_dmi(target);
+ LOG_DEBUG("ASSERTING NDRESET");
+ uint32_t control = dmi_read(target, DMI_DMCONTROL);
+ control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
+ if (target->reset_halt) {
+ LOG_DEBUG("TARGET RESET HALT SET, ensuring halt is set during reset.");
+ control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
+ } else {
+ LOG_DEBUG("TARGET RESET HALT NOT SET");
+ control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
+ }
- dmi_write(target, DMI_DMCONTROL,
- control);
+ dmi_write(target, DMI_DMCONTROL, control);
- return ERROR_OK;
+ return ERROR_OK;
}
static int deassert_reset(struct target *target)
{
- RISCV_INFO(r);
- RISCV013_INFO(info);
-
- select_dmi(target);
-
- /*FIXME -- this only works for Single Hart*/
- assert(r->current_hartid == 0);
-
- /*FIXME -- is there bookkeeping we need to do here*/
-
- uint32_t control = dmi_read(target, DMI_DMCONTROL);
-
- // Clear the reset, but make sure haltreq is still set
- if (target->reset_halt) {
- control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
- }
-
- control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
- dmi_write(target, DMI_DMCONTROL, control);
-
- uint32_t status;
- int dmi_busy_delay = info->dmi_busy_delay;
- if (target->reset_halt) {
- LOG_DEBUG("DEASSERTING RESET, waiting for hart to be halted.");
- do {
- status = dmi_read(target, DMI_DMSTATUS);
- } while (get_field(status, DMI_DMSTATUS_ALLHALTED) == 0);
- } else {
- LOG_DEBUG("DEASSERTING RESET, waiting for hart to be running.");
- do {
- status = dmi_read(target, DMI_DMSTATUS);
- if (get_field(status, DMI_DMSTATUS_ANYHALTED) ||
- get_field(status, DMI_DMSTATUS_ANYUNAVAIL)) {
- LOG_ERROR("Unexpected hart status during reset.");
- abort();
- }
- } while (get_field(status, DMI_DMSTATUS_ALLRUNNING) == 0);
- }
- info->dmi_busy_delay = dmi_busy_delay;
- return ERROR_OK;
+ RISCV_INFO(r);
+ RISCV013_INFO(info);
+ select_dmi(target);
+
+ /*FIXME -- this only works for Single Hart*/
+ assert(r->current_hartid == 0);
+
+ /*FIXME -- is there bookkeeping we need to do here*/
+
+ uint32_t control = dmi_read(target, DMI_DMCONTROL);
+
+ // Clear the reset, but make sure haltreq is still set
+ if (target->reset_halt) {
+ control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
+ }
+
+ control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
+ dmi_write(target, DMI_DMCONTROL, control);
+
+ uint32_t status;
+ int dmi_busy_delay = info->dmi_busy_delay;
+ if (target->reset_halt) {
+ LOG_DEBUG("DEASSERTING RESET, waiting for hart to be halted.");
+ do {
+ status = dmi_read(target, DMI_DMSTATUS);
+ } while (get_field(status, DMI_DMSTATUS_ALLHALTED) == 0);
+ } else {
+ LOG_DEBUG("DEASSERTING RESET, waiting for hart to be running.");
+ do {
+ status = dmi_read(target, DMI_DMSTATUS);
+ if (get_field(status, DMI_DMSTATUS_ANYHALTED) ||
+ get_field(status, DMI_DMSTATUS_ANYUNAVAIL)) {
+ LOG_ERROR("Unexpected hart status during reset.");
+ abort();
+ }
+ } while (get_field(status, DMI_DMSTATUS_ALLRUNNING) == 0);
+ }
+ info->dmi_busy_delay = dmi_busy_delay;
+ return ERROR_OK;
}
static int read_memory(struct target *target, target_addr_t address,
@@ -1317,8 +1315,8 @@ static int read_memory(struct target *target, target_addr_t address,
assert(prev_addr < cur_addr);
prev_addr = cur_addr;
riscv_addr_t start = (cur_addr - address) / size;
- assert (cur_addr >= address);
- struct riscv_batch *batch = riscv_batch_alloc(
+ assert (cur_addr >= address);
+ struct riscv_batch *batch = riscv_batch_alloc(
target,
32,
info->dmi_busy_delay + info->ac_busy_delay);
@@ -1371,10 +1369,10 @@ static int read_memory(struct target *target, target_addr_t address,
riscv_batch_free(batch);
- // Note that if the scan resulted in a Busy DMI response, it
- // is this read to abstractcs that will cause the dmi_busy_delay
- // to be incremented if necessary. The loop condition above
- // catches the case where no writes went through at all.
+ // Note that if the scan resulted in a Busy DMI response, it
+ // is this read to abstractcs that will cause the dmi_busy_delay
+ // to be incremented if necessary. The loop condition above
+ // catches the case where no writes went through at all.
uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
@@ -1512,8 +1510,8 @@ static int write_memory(struct target *target, target_addr_t address,
while ((cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) {
LOG_DEBUG("transferring burst starting at address 0x%016lx", cur_addr);
riscv_addr_t start = (cur_addr - address) / size;
- assert (cur_addr > address);
- struct riscv_batch *batch = riscv_batch_alloc(
+ assert (cur_addr > address);
+ struct riscv_batch *batch = riscv_batch_alloc(
target,
32,
info->dmi_busy_delay + info->ac_busy_delay);
@@ -1555,10 +1553,10 @@ static int write_memory(struct target *target, target_addr_t address,
riscv_batch_run(batch);
riscv_batch_free(batch);
- // Note that if the scan resulted in a Busy DMI response, it
- // is this read to abstractcs that will cause the dmi_busy_delay
- // to be incremented if necessary. The loop condition above
- // catches the case where no writes went through at all.
+ // Note that if the scan resulted in a Busy DMI response, it
+ // is this read to abstractcs that will cause the dmi_busy_delay
+ // to be incremented if necessary. The loop condition above
+ // catches the case where no writes went through at all.
uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
@@ -1819,26 +1817,26 @@ int riscv013_execute_debug_buffer(struct target *target)
void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
{
- RISCV013_INFO(info);
- buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
- buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, d);
- buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
+ RISCV013_INFO(info);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_WRITE);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, d);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
}
void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a)
{
- RISCV013_INFO(info);
- buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
- buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
- buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
+ RISCV013_INFO(info);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_READ);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, a);
}
void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
{
- RISCV013_INFO(info);
- buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
- buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
- buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
+ RISCV013_INFO(info);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH, DMI_OP_NOP);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH, 0);
+ buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
}
int riscv013_dmi_write_u64_bits(struct target *target)
@@ -1849,19 +1847,19 @@ int riscv013_dmi_write_u64_bits(struct target *target)
void riscv013_reset_current_hart(struct target *target)
{
- select_dmi(target);
- uint32_t control = dmi_read(target, DMI_DMCONTROL);
- control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
- control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
- dmi_write(target, DMI_DMCONTROL, control);
+ select_dmi(target);
+ uint32_t control = dmi_read(target, DMI_DMCONTROL);
+ control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
+ control = set_field(control, DMI_DMCONTROL_HALTREQ, 1);
+ dmi_write(target, DMI_DMCONTROL, control);
- control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
- dmi_write(target, DMI_DMCONTROL, control);
+ control = set_field(control, DMI_DMCONTROL_NDMRESET, 0);
+ dmi_write(target, DMI_DMCONTROL, control);
- while (get_field(dmi_read(target, DMI_DMSTATUS), DMI_DMSTATUS_ALLHALTED) == 0);
+ while (get_field(dmi_read(target, DMI_DMSTATUS), DMI_DMSTATUS_ALLHALTED) == 0);
- control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
- dmi_write(target, DMI_DMCONTROL, control);
+ control = set_field(control, DMI_DMCONTROL_HALTREQ, 0);
+ dmi_write(target, DMI_DMCONTROL, control);
}
/* Helper Functions. */
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index e578b9c..31a6db6 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -172,18 +172,18 @@ enum {
uint8_t ir_dtmcontrol[1] = {DTMCONTROL};
struct scan_field select_dtmcontrol = {
- .in_value = NULL,
- .out_value = ir_dtmcontrol
+ .in_value = NULL,
+ .out_value = ir_dtmcontrol
};
uint8_t ir_dbus[1] = {DBUS};
struct scan_field select_dbus = {
- .in_value = NULL,
- .out_value = ir_dbus
+ .in_value = NULL,
+ .out_value = ir_dbus
};
uint8_t ir_idcode[1] = {0x1};
struct scan_field select_idcode = {
- .in_value = NULL,
- .out_value = ir_idcode
+ .in_value = NULL,
+ .out_value = ir_idcode
};
struct trigger {
@@ -309,10 +309,10 @@ static int oldriscv_step(struct target *target, int current, uint32_t address,
}
static int old_or_new_riscv_step(
- struct target *target,
- int current,
- target_addr_t address,
- int handle_breakpoints
+ struct target *target,
+ int current,
+ target_addr_t address,
+ int handle_breakpoints
){
RISCV_INFO(r);
if (r->is_halted == NULL)
@@ -326,7 +326,7 @@ static int riscv_examine(struct target *target)
{
LOG_DEBUG("riscv_examine()");
if (target_was_examined(target)) {
- LOG_DEBUG("Target was already examined.\n");
+ LOG_DEBUG("Target was already examined.\n");
return ERROR_OK;
}
@@ -375,14 +375,14 @@ static int old_or_new_riscv_halt(struct target *target)
static int oldriscv_assert_reset(struct target *target)
{
- LOG_DEBUG("RISCV ASSERT RESET");
+ LOG_DEBUG("RISCV ASSERT RESET");
struct target_type *tt = get_target_type(target);
return tt->assert_reset(target);
}
static int oldriscv_deassert_reset(struct target *target)
{
- LOG_DEBUG("RISCV DEASSERT RESET");
+ LOG_DEBUG("RISCV DEASSERT RESET");
struct target_type *tt = get_target_type(target);
return tt->deassert_reset(target);
}
@@ -415,11 +415,11 @@ static int oldriscv_resume(struct target *target, int current, uint32_t address,
}
static int old_or_new_riscv_resume(
- struct target *target,
- int current,
- target_addr_t address,
- int handle_breakpoints,
- int debug_execution
+ struct target *target,
+ int current,
+ target_addr_t address,
+ int handle_breakpoints,
+ int debug_execution
){
RISCV_INFO(r);
if (r->is_halted == NULL)
@@ -626,11 +626,11 @@ memory. Not yet implemented.
*/
static int riscv_checksum_memory(struct target *target,
- target_addr_t address, uint32_t count,
- uint32_t* checksum)
+ target_addr_t address, uint32_t count,
+ uint32_t* checksum)
{
- *checksum = 0xFFFFFFFF;
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ *checksum = 0xFFFFFFFF;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/* Should run code on the target to check whether a memory
@@ -640,13 +640,13 @@ Not yet implemented.
*/
int riscv_blank_check_memory(struct target * target,
target_addr_t address,
- uint32_t count,
- uint32_t * blank,
+ uint32_t count,
+ uint32_t * blank,
uint8_t erased_value)
{
- *blank = 0;
+ *blank = 0;
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/*** OpenOCD Helper Functions ***/
@@ -760,11 +760,11 @@ int riscv_openocd_halt(struct target *target)
}
int riscv_openocd_resume(
- struct target *target,
- int current,
- target_addr_t address,
- int handle_breakpoints,
- int debug_execution
+ struct target *target,
+ int current,
+ target_addr_t address,
+ int handle_breakpoints,
+ int debug_execution
) {
LOG_DEBUG("resuming all harts");
@@ -785,10 +785,10 @@ int riscv_openocd_resume(
}
int riscv_openocd_step(
- struct target *target,
- int current,
- target_addr_t address,
- int handle_breakpoints
+ struct target *target,
+ int current,
+ target_addr_t address,
+ int handle_breakpoints
) {
LOG_DEBUG("stepping rtos hart");
@@ -1026,9 +1026,9 @@ void riscv_set_current_hartid(struct target *target, int hartid)
/* Avoid invalidating the register cache all the time. */
if (r->registers_initialized
- && (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
- && target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target)
- && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
+ && (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
+ && target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target)
+ && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
LOG_DEBUG("registers already initialized, skipping");
return;
} else