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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-25 13:12:21 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-25 13:14:31 -0700 |
| commit | ab77c5d7921f779d77c72212937aa8544dbfc1b4 (patch) | |
| tree | 4ad0bf3f14739f133b16ee2b2279f76e768715c5 | |
| parent | faa6123e36a4a6a7a1a4c8190a37ae5bfbe183bd (diff) | |
| download | riscv-openocd-ab77c5d7921f779d77c72212937aa8544dbfc1b4.zip riscv-openocd-ab77c5d7921f779d77c72212937aa8544dbfc1b4.tar.gz riscv-openocd-ab77c5d7921f779d77c72212937aa8544dbfc1b4.tar.bz2 | |
Invalidate the register cache when rtos_hartid==-1
This means I don't know what hart to look at, so I might as well
invalidate the register cache. Without this, you might get stale
registers the first time you ask for them.
| -rw-r--r-- | src/target/riscv/riscv.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index f89df6e..c232204 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1017,7 +1017,10 @@ void riscv_set_current_hartid(struct target *target, int hartid) return; /* Avoid invalidating the register cache all the time. */ - if (r->registers_initialized && (!riscv_rtos_enabled(target) || (previous_hartid == hartid)) && target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target)) { + if (r->registers_initialized + && (!riscv_rtos_enabled(target) || (previous_hartid == hartid)) + && target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target) + && (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) { LOG_DEBUG("registers already initialized, skipping"); return; } else |