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| author | Tim Newsome <tim@sifive.com> | 2019-02-14 12:53:28 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-14 12:53:28 -0800 |
| commit | fa8b8e0d6a92d4e7e8876c996d80d148e9dea231 (patch) | |
| tree | 266dc7bf11d163f14a9a69fdcbcc720361d95e6f | |
| parent | 80ef54dba2411f9354b3793d5832c5d8ad871b4b (diff) | |
| download | riscv-openocd-fa8b8e0d6a92d4e7e8876c996d80d148e9dea231.zip riscv-openocd-fa8b8e0d6a92d4e7e8876c996d80d148e9dea231.tar.gz riscv-openocd-fa8b8e0d6a92d4e7e8876c996d80d148e9dea231.tar.bz2 | |
Fix cut and paste error in docs. (#352)
Fixes #349.
Change-Id: I5cfd5b28eef463cfa1faa3d1d766eb3e3f52904a
| -rw-r--r-- | doc/openocd.texi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 168e660..7dfd977 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -9117,7 +9117,7 @@ command can be used if OpenOCD gets this wrong, or a target implements custom CSRs. @end deffn -@deffn Command {riscv expose_csrs} n0[-m0][,n1[-m1]]... +@deffn Command {riscv expose_custom} n0[-m0][,n1[-m1]]... The RISC-V Debug Specification allows targets to expose custom registers through abstract commands. (See Section 3.5.1.1 in that document.) This command configures a list of inclusive ranges of those registers to expose. Number 0 |