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authorTim Newsome <tim@sifive.com>2018-11-05 11:48:52 -0800
committerGitHub <noreply@github.com>2018-11-05 11:48:52 -0800
commitca1a1f8db73559a98c878f31952ca850e6d1cf73 (patch)
tree5adb84763d05216089f898dbd53fdf5fb97a97a2
parent60368dd62e29fe728e9987010bc9c8b0b5815af3 (diff)
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Complete single step before returning. (#319)
This fixes the following error, that has been reported occasionally: Error: 34072 2712 riscv-011.c:1175 reg_cache_get(): Register cache entry for 0 is invalid! openocd: ../src/target/riscv/riscv-011.c:1176: reg_cache_get: Assertion `r->valid' failed. The problem was that we'd tell the target to step, and then gdb (which assumed the target halted already) asked to read a register before the target had actually halted. With this fix the target is actually halted, and everything works. Change-Id: Icfcef456f3cec4bb352fb90186f5bbabb00a5ff8
-rw-r--r--src/target/riscv/riscv-011.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index a9364d7..4ddc0e9 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -1451,7 +1451,7 @@ static int step(struct target *target, int current, target_addr_t address,
if (result != ERROR_OK)
return result;
} else {
- return resume(target, 0, true);
+ return full_step(target, false);
}
return ERROR_OK;