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| author | Tim Newsome <tim@sifive.com> | 2022-07-18 09:20:22 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-07-18 09:20:22 -0700 |
| commit | 969f112321361065e9f8671c4b04ea510e8d06e2 (patch) | |
| tree | e59054689ddb40033217cd402d24c2571c898a26 | |
| parent | aaf0620479bf8958040ab6483a579244584c9904 (diff) | |
| download | riscv-openocd-969f112321361065e9f8671c4b04ea510e8d06e2.zip riscv-openocd-969f112321361065e9f8671c4b04ea510e8d06e2.tar.gz riscv-openocd-969f112321361065e9f8671c4b04ea510e8d06e2.tar.bz2 | |
Update debug_defines.h. (#711)
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.
Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
| -rw-r--r-- | src/target/riscv/debug_defines.h | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h index 1c74592..8113d47 100644 --- a/src/target/riscv/debug_defines.h +++ b/src/target/riscv/debug_defines.h @@ -1,7 +1,6 @@ /* * This file is auto-generated by running 'make debug_defines.h' in - * https://github.com/riscv/riscv-debug-spec/ (182b9c4) - * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0) + * https://github.com/riscv/riscv-debug-spec/ (d749752) */ #define DTM_IDCODE 0x01 @@ -313,36 +312,35 @@ * * When there are multiple reasons to enter Debug Mode in a single * cycle, hardware should set \FcsrDcsrCause to the cause with the highest - * priority. + * priority. See table~\ref{tab:dcsrcausepriority} for priorities. */ #define CSR_DCSR_CAUSE_OFFSET 6 #define CSR_DCSR_CAUSE_LENGTH 3 #define CSR_DCSR_CAUSE 0x1c0 /* - * ebreak: An {\tt ebreak} instruction was executed. (priority 3) + * ebreak: An {\tt ebreak} instruction was executed. */ #define CSR_DCSR_CAUSE_EBREAK 1 /* - * trigger: A Trigger Module trigger fired with action=1. (priority 4) + * trigger: A Trigger Module trigger fired with action=1. */ #define CSR_DCSR_CAUSE_TRIGGER 2 /* * haltreq: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq. - * (priority 1) */ #define CSR_DCSR_CAUSE_HALTREQ 3 /* - * step: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest) + * step: The hart single stepped because \FcsrDcsrStep was set. */ #define CSR_DCSR_CAUSE_STEP 4 /* * resethaltreq: The hart halted directly out of reset due to \Fresethaltreq. It - * is also acceptable to report 3 when this happens. (priority 2) + * is also acceptable to report 3 when this happens. */ #define CSR_DCSR_CAUSE_RESETHALTREQ 5 /* - * group: The hart halted because it's part of a halt group. (priority 5, - * highest) Harts may report 3 for this cause instead. + * group: The hart halted because it's part of a halt group. + * Harts may report 3 for this cause instead. */ #define CSR_DCSR_CAUSE_GROUP 6 /* |