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| author | Tim Newsome <tim@sifive.com> | 2017-12-11 12:52:48 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-12-19 10:41:48 -0800 |
| commit | 46715c7d8adfda02d50fcd9d19ff8899ab1f69bf (patch) | |
| tree | bce678595455c7b4b97bdc8ed5d481a5913fe54c | |
| parent | 120477b2a21d20302df86804f25fb8425be558e6 (diff) | |
| download | riscv-openocd-46715c7d8adfda02d50fcd9d19ff8899ab1f69bf.zip riscv-openocd-46715c7d8adfda02d50fcd9d19ff8899ab1f69bf.tar.gz riscv-openocd-46715c7d8adfda02d50fcd9d19ff8899ab1f69bf.tar.bz2 | |
Remove no-longer-true comment.
Change-Id: I888680e73682582438a0de0496238867f1604754
| -rw-r--r-- | src/target/riscv/riscv.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index f1152a3..ef241af 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1403,7 +1403,6 @@ void riscv_invalidate_register_cache(struct target *target) { RISCV_INFO(r); - /* Update the register list's widths. */ register_cache_invalidate(target->reg_cache); for (size_t i = 0; i < GDB_REGNO_COUNT; ++i) { struct reg *reg = &target->reg_cache->reg_list[i]; |