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author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-25 13:10:28 -0700 |
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committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-05-25 13:14:31 -0700 |
commit | faa6123e36a4a6a7a1a4c8190a37ae5bfbe183bd (patch) | |
tree | 7c6976acedc99b72af7a1a77eb3aff26309a7738 | |
parent | a1e07e58f4edbea92830fc75965a18b7b5030e17 (diff) | |
download | riscv-openocd-faa6123e36a4a6a7a1a4c8190a37ae5bfbe183bd.zip riscv-openocd-faa6123e36a4a6a7a1a4c8190a37ae5bfbe183bd.tar.gz riscv-openocd-faa6123e36a4a6a7a1a4c8190a37ae5bfbe183bd.tar.bz2 |
Invalidate the register cache on step, resume, reset
I thought OpenOCD did this, but it looks like that doesn't happen when
runningi in RTOS mode. With this I can get to the end of most of the
RTOS tests, but they SIGINT instead of exiting.
-rw-r--r-- | src/target/riscv/riscv.c | 11 | ||||
-rw-r--r-- | src/target/riscv/riscv.h | 3 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index c083636..f89df6e 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -914,6 +914,7 @@ int riscv_resume_all_harts(struct target *target) riscv_resume_one_hart(target, riscv_current_hartid(target)); } + riscv_invalidate_register_cache(target); return ERROR_OK; } @@ -941,6 +942,7 @@ int riscv_reset_all_harts(struct target *target) riscv_reset_one_hart(target, riscv_current_hartid(target)); } + riscv_invalidate_register_cache(target); return ERROR_OK; } @@ -973,8 +975,10 @@ int riscv_step_rtos_hart(struct target *target) LOG_DEBUG("stepping hart %d", hartid); assert(riscv_is_halted(target)); + riscv_invalidate_register_cache(target); r->on_step(target); r->step_current_hart(target); + riscv_invalidate_register_cache(target); r->on_halt(target); assert(riscv_is_halted(target)); return ERROR_OK; @@ -1019,6 +1023,13 @@ void riscv_set_current_hartid(struct target *target, int hartid) } else LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target)); + riscv_invalidate_register_cache(target); +} + +void riscv_invalidate_register_cache(struct target *target) +{ + RISCV_INFO(r); + /* Update the register list's widths. */ register_cache_invalidate(target->reg_cache); for (size_t i = 0; i < GDB_REGNO_COUNT; ++i) { diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index a51456f..7b27b35 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -211,4 +211,7 @@ void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a); int riscv_dmi_write_u64_bits(struct target *target); +/* Invalidates the register cache. */ +void riscv_invalidate_register_cache(struct target *target); + #endif |