| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-01-22 | Update Go instruction encoding generation (#34) | Joel Sing | 1 | -4/+4 |
| 2020-11-08 | Support generating Rust code (#52) | Ngo Iok Ui (Wu Yu Wei) | 1 | -0/+13 |
| 2020-10-14 | Adding four trigger CSRs to the list (#50) | Jan Matyas | 1 | -0/+4 |
| 2020-07-31 | hyperviosr: add csr mask and interrupt macro name | Chih-Min Chao | 1 | -1/+5 |
| 2020-04-14 | rvv: add new vcsr for vector spec 0.9 (#42) | Chih-Min Chao | 1 | -0/+1 |
| 2020-03-31 | update csr to draft-20200326-af69f79 (#39) | Chih-Min Chao | 1 | -1/+16 |
| 2020-03-29 | Using OrderedDict to keep encodings for match/mask. (#38) | Kito Cheng | 1 | -2/+3 |
| 2020-02-28 | Add mcountinhibit CSR | Andrew Waterman | 1 | -0/+1 |
| 2020-02-24 | Add N-extension CSRs and status bits. (#37) | michael-roe | 1 | -0/+2 |
| 2019-11-28 | rvv: add vleb csr register and mstatus.vs field | Chih-Min Chao | 1 | -0/+1 |
| 2019-08-03 | Fix crash introduced by #30 | Andrew Waterman | 1 | -1/+1 |
| 2019-08-03 | (Partially) fix #30 (#31) | Tommy Thorn | 1 | -0/+1089 |
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index : riscv-tools/riscv-opcodes.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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path: root/parse_opcodes