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AgeCommit message (Expand)AuthorFilesLines
2019-05-16rvv: add vector register field and control registerChih-Min Chao1-1/+18
2019-05-14zimm -> uimm in CSR instruction listingAndrew Waterman1-2/+2
2019-04-26Create RVQ listing in latex tableAndrew Waterman1-0/+16
2019-04-22Add missing N-extension CSRsAndrew Waterman1-0/+8
2019-02-28Read opcodes from files (#23)Pavel I. Kryukov1-61/+74
2019-02-11Add SystemVerilog generation (#24)Florian Zaruba1-0/+21
2019-01-22Add tentative CSR assignment for fast-interrupt group's CLIC proposalAndrew Waterman1-0/+17
2019-01-21Add tentative hypervisor CSR and instruction encodingsAndrew Waterman1-1/+19
2018-11-20Don't label latex tablesAndrew Waterman1-1/+0
2018-11-20Exclude ECALL/EBREAK from privileged instruction tableAndrew Waterman1-3/+1
2018-11-19Modernize to Python 3 (#22)Pavel I. Kryukov1-111/+114
2018-11-06Separate FENCE.I and CSRRx from RV32I tableAndrew Waterman1-9/+15
2018-09-20Add header following Go convention for generated code (#21)Tobias Klauser1-1/+1
2018-08-25Improve TeX output for FENCE instructionsAndrew Waterman1-1/+1
2018-08-06FENCE has a field called FM in bits 31:28Andrew Waterman1-1/+2
2018-07-17Make the hashbang portable (#20)Edward Tomasz Napierała1-1/+1
2017-11-27Rename sptbr to satp and sbadaddr to stvalAndrew Waterman1-3/+3
2017-05-17Merge remote-tracking branch 'origin/priv-1.10'Palmer Dabbelt1-15/+38
2017-05-07SB->B; UJ->JAndrew Waterman1-2/+2
2017-04-25Add ECALL/EBREAK to privileged instruction tableAndrew Waterman1-0/+2
2017-04-25FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.XAndrew Waterman1-2/+2
2017-04-25Remove hret instructionAndrew Waterman1-1/+1
2017-03-31Support generating Go code (#3)Benjamin Barenblat1-0/+41
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-3/+6
2017-03-23Add PMPAndrew Waterman1-0/+20
2017-03-09New counter-enable mechanismAndrew Waterman1-2/+2
2017-02-20Remove sfence.vm and add sfence.vmaAndrew Waterman1-5/+3
2016-12-21Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 spaceKito Cheng1-1/+1
2016-08-26Renumber misa; add performance counter CSRsAndrew Waterman1-33/+154
2016-08-25Re-rename trigger registers to be 1-basedAndrew Waterman1-3/+3
2016-08-25Make hardware triggers match latest spec.Tim Newsome1-4/+4
2016-06-30Remove instructions from privilege spec that are already in user specAndrew Waterman1-5/+2
2016-06-17Remove sasid (it's merged into sptbr now)Andrew Waterman1-1/+0
2016-06-08Add breakpoint CSRsAndrew Waterman1-0/+4
2016-06-01Add dret instruction and debug CSRs. (#5)Tim Newsome1-0/+3
2016-05-13Remove arg lists from latex tablesAndrew Waterman1-42/+1
2016-05-02Remove mipi registersAndrew Waterman1-1/+0
2016-05-02Remove tohost/fromhostAndrew Waterman1-2/+0
2016-04-30Remove mcfgaddr; change memory mapAndrew Waterman1-2/+1
2016-04-30Remove mtimecmpAndrew Waterman1-2/+0
2016-04-30ERET -> xRETAndrew Waterman1-1/+1
2016-04-06Remove nonstandard stats, uarch CSRsAndrew Waterman1-21/+0
2016-03-03Update CSR encodingAndrew Waterman1-0/+19
2016-02-28WIP on priv spec v1.9Andrew Waterman1-30/+14
2016-02-28WIP on priv spec v1.9Andrew Waterman1-16/+15
2016-02-05WIP on priv spec v1.9Andrew Waterman1-5/+4
2015-11-12add miobase, mipi; drop send_ipiAndrew Waterman1-1/+2
2015-09-28In C headers, keep instructions in original input orderAndrew Waterman1-2/+2
2015-09-08Use BitPat instead of Bits for Chisel3Andrew Waterman1-1/+1
2015-09-08update to latest RVC proposalAndrew Waterman1-2/+5
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