| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2011-04-07 | [pk,sim] fixed parse-opcodes bug | Andrew Waterman | 1 | -2/+2 |
| 2011-04-05 | [opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in... | Yunsup Lee | 1 | -16/+17 |
| 2011-04-04 | [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.) | Yunsup Lee | 1 | -0/+1 |
| 2011-04-04 | [opcodes,pk,sim,xcc] add vector mem instructions | Yunsup Lee | 1 | -0/+2 |
| 2011-03-25 | [opcodes] fixed up instruction table | Andrew Waterman | 1 | -207/+197 |
| 2011-03-25 | [xcc,pk,opcodes,sim] updated encoding/insn names | Andrew Waterman | 1 | -2/+3 |
| 2011-01-31 | [opcodes] fixed verilog generation for shifts | Andrew Waterman | 1 | -3/+3 |
| 2011-01-25 | [opcodes,pk,sim,xcc] great renumbering of 2011, part deux | Andrew Waterman | 1 | -23/+22 |
| 2011-01-20 | [sim, pk, xcc, opcodes] great instruction renaming of 2011 | Andrew Waterman | 1 | -0/+1 |
| 2011-01-03 | [opcodes,pk,sim,xcc] flip fields to favor little endian | Yunsup Lee | 1 | -59/+59 |
| 2010-11-21 | [opcodes, pk, sim, xcc] Tweaked FP encoding | Andrew Waterman | 1 | -90/+67 |
| 2010-11-21 | [opcodes] generate latex and verilog correctly | Andrew Waterman | 1 | -125/+164 |
| 2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -33/+35 |
| 2010-11-21 | [opcodes, pk, sim, xcc] made jumps shorter and PC-relative | Andrew Waterman | 1 | -6/+6 |
| 2010-10-31 | [opcodes] add latex table for rm stuff | Yunsup Lee | 1 | -60/+145 |
| 2010-10-25 | [sim,xcc,pk,opcodes] static rounding modes for FP insns | Andrew Waterman | 1 | -1/+41 |
| 2010-10-20 | [opcodes] changed formatting of optab section headers | Andrew Waterman | 1 | -6/+6 |
| 2010-10-05 | [opcodes] updated parse-opcodes for latex tables | Yunsup Lee | 1 | -50/+100 |
| 2010-10-05 | [opcodes] update parse-opcodes | Yunsup Lee | 1 | -20/+20 |
| 2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -38/+36 |
| 2010-09-12 | [opcodes] fixed tex table for ish,ishw types | Yunsup Lee | 1 | -41/+38 |
| 2010-09-12 | [opcodes] change rsh to ish types | Yunsup Lee | 1 | -9/+9 |
| 2010-09-12 | [opcodes] fixed verilog generation for ish,ishw types | Yunsup Lee | 1 | -8/+8 |
| 2010-09-12 | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 1 | -2/+2 |
| 2010-09-12 | add -verilog option | Yunsup Lee | 1 | -0/+111 |
| 2010-09-10 | [opcodes] latex table generation added, new opcode mapping | Yunsup Lee | 1 | -142/+500 |
| 2010-09-06 | [sim] added atomic memory operations | Andrew Waterman | 1 | -1/+0 |
| 2010-08-22 | [xcc,sim] added fused multiply-add and its cousins | Andrew Waterman | 1 | -0/+1 |
| 2010-08-03 | [sim,xcc] removed sll32/srl32/sra32 opcodes | Andrew Waterman | 1 | -1/+2 |
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -89/+137 |
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+115 |
