| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-11-06 | CSRRx is called Zicsrv | Andrew Waterman | 1 | -1/+1 | |
| 2018-11-06 | Split V table from rest of table | Andrew Waterman | 1 | -1/+4 | |
| Generate it with the command cat opcodes-v | ./parse-opcodes -vtex | |||||
| 2018-11-06 | Updates from most recent meeting | Andrew Waterman | 1 | -3/+6 | |
| 2018-11-06 | V extension WIP | Andrew Waterman | 1 | -6/+132 | |
| 2018-11-06 | Separate FENCE.I and CSRRx from RV32I table | Andrew Waterman | 1 | -9/+15 | |
| 2018-09-20 | Add header following Go convention for generated code (#21) | Tobias Klauser | 1 | -1/+1 | |
| Go has a convention for generated code comments (https://golang.org/s/generatedcode), i.e. they must match the regex ^// Code generated .* DO NOT EDIT\.$ Adjust the generated header to follow this convention. | |||||
| 2018-08-25 | Improve TeX output for FENCE instructions | Andrew Waterman | 1 | -1/+1 | |
| 2018-08-06 | FENCE has a field called FM in bits 31:28 | Andrew Waterman | 1 | -1/+2 | |
| 2018-07-17 | Make the hashbang portable (#20) | Edward Tomasz Napierała | 1 | -1/+1 | |
| Not all systems put Python binary in /usr/bin; fix it as usual by using env(1) | |||||
| 2017-11-27 | Rename sptbr to satp and sbadaddr to stval | Andrew Waterman | 1 | -3/+3 | |
| Closes #17 | |||||
| 2017-05-17 | Merge remote-tracking branch 'origin/priv-1.10' | Palmer Dabbelt | 1 | -15/+38 | |
| 2017-05-07 | SB->B; UJ->J | Andrew Waterman | 1 | -2/+2 | |
| 2017-04-25 | Add ECALL/EBREAK to privileged instruction table | Andrew Waterman | 1 | -0/+2 | |
| 2017-04-25 | FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X | Andrew Waterman | 1 | -2/+2 | |
| 2017-04-25 | Remove hret instruction | Andrew Waterman | 1 | -1/+1 | |
| 2017-03-31 | Support generating Go code (#3) | Benjamin Barenblat | 1 | -0/+41 | |
| * Support generating Go code Generate Go code for the RISC-V Go port <https://github.com/riscv/riscv-go>. * Clarify use of yank in Go backend * Go: Also generate funct3, csr, and funct7 encodings * Go: Emit all instructions Changes to the RISC-V Go implementation obviate the need for GO_UNUSED_INSTRUCTIONS. * Go: Print CSRs as signed values * Go: Update parse-opcodes to use obj.As See https://github.com/golang/go/commit/0d9258a830c585. * Go: Return errors out of band * Go: Return 'ok' status instead of 'err' status Also clean up imports. * Go: Make gofmt-clean * Go: Return rs2 value for each instructions Some binary floating-point instructions (ab)use the rs2 value to hold additional instruction data, so we need that data in the Go assembler. | |||||
| 2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 1 | -3/+6 | |
| 2017-03-23 | Add PMP | Andrew Waterman | 1 | -0/+20 | |
| 2017-03-09 | New counter-enable mechanism | Andrew Waterman | 1 | -2/+2 | |
| 2017-02-20 | Remove sfence.vm and add sfence.vma | Andrew Waterman | 1 | -5/+3 | |
| 2016-12-21 | Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space | Kito Cheng | 1 | -1/+1 | |
| 2016-08-26 | Renumber misa; add performance counter CSRs | Andrew Waterman | 1 | -33/+154 | |
| 2016-08-25 | Re-rename trigger registers to be 1-based | Andrew Waterman | 1 | -3/+3 | |
| 2016-08-25 | Make hardware triggers match latest spec. | Tim Newsome | 1 | -4/+4 | |
| 2016-06-30 | Remove instructions from privilege spec that are already in user spec | Andrew Waterman | 1 | -5/+2 | |
| 2016-06-17 | Remove sasid (it's merged into sptbr now) | Andrew Waterman | 1 | -1/+0 | |
| 2016-06-08 | Add breakpoint CSRs | Andrew Waterman | 1 | -0/+4 | |
| 2016-06-01 | Add dret instruction and debug CSRs. (#5) | Tim Newsome | 1 | -0/+3 | |
| 2016-05-13 | Remove arg lists from latex tables | Andrew Waterman | 1 | -42/+1 | |
| 2016-05-02 | Remove mipi registers | Andrew Waterman | 1 | -1/+0 | |
| IPI pending registers will live outside the core, so they can cause wakeup. | |||||
| 2016-05-02 | Remove tohost/fromhost | Andrew Waterman | 1 | -2/+0 | |
| 2016-04-30 | Remove mcfgaddr; change memory map | Andrew Waterman | 1 | -2/+1 | |
| 2016-04-30 | Remove mtimecmp | Andrew Waterman | 1 | -2/+0 | |
| 2016-04-30 | ERET -> xRET | Andrew Waterman | 1 | -1/+1 | |
| 2016-04-06 | Remove nonstandard stats, uarch CSRs | Andrew Waterman | 1 | -21/+0 | |
| 2016-03-03 | Update CSR encoding | Andrew Waterman | 1 | -0/+19 | |
| 2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -30/+14 | |
| 2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -16/+15 | |
| 2016-02-05 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -5/+4 | |
| 2015-11-12 | add miobase, mipi; drop send_ipi | Andrew Waterman | 1 | -1/+2 | |
| 2015-09-28 | In C headers, keep instructions in original input order | Andrew Waterman | 1 | -2/+2 | |
| 2015-09-08 | Use BitPat instead of Bits for Chisel3 | Andrew Waterman | 1 | -1/+1 | |
| 2015-09-08 | update to latest RVC proposal | Andrew Waterman | 1 | -2/+5 | |
| 2015-07-28 | Fix DECLARE_CAUSE macros | Andrew Waterman | 1 | -1/+1 | |
| 2015-07-05 | New machine-mode timer facility | Andrew Waterman | 1 | -1/+1 | |
| 2015-05-09 | Update to privileged architecture version 1.7 | Andrew Waterman | 1 | -25/+96 | |
| 2015-03-30 | RVC draft | Andrew Waterman | 1 | -13/+2 | |
| 2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 1 | -8/+6 | |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -27/+53 | |
| 2014-04-03 | Move stats register | Stephen Twigg | 1 | -1/+1 | |
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index : riscv-tools/riscv-opcodes.git | |
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path: root/parse-opcodes