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AgeCommit message (Collapse)AuthorFilesLines
2013-11-22add missing imm for storesYunsup Lee1-0/+1
2013-10-29changes to the instr-tableYunsup Lee1-14/+16
2013-10-10revamp hwacha-v3 opcodesYunsup Lee1-2/+1
2013-09-21Fix funct field in tables.Andrew Waterman1-1/+1
2013-09-21Update ISA encodingAndrew Waterman1-191/+238
2013-08-07hwacha v3: inst format follows the new rocket accelerator extensionsYunsup Lee1-0/+2
2013-08-06Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman1-2/+2
2013-07-31HW ignores upper bits of fence, but SW supplies 0Andrew Waterman1-10/+14
2013-07-26tweaksYunsup Lee1-11/+13
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-4/+4
2013-07-25Refactor parse-opcodesAndrew Waterman1-303/+84
2013-04-17add auipc, lr, scAndrew Waterman1-0/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+791
2011-06-19Renamed packagesAndrew Waterman1-791/+0
2011-06-19[riscv-isa-run] code cleanup; added READMEAndrew Waterman1-3/+4
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-59/+5
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-46/+59
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee1-2/+2
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee1-3/+28
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman1-26/+1
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman1-0/+1
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman1-0/+4
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-1/+4
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-1/+5
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-4/+7
2011-04-07[pk,sim] fixed parse-opcodes bugAndrew Waterman1-2/+2
was causing spurious illegal instruction traps
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵Yunsup Lee1-16/+17
instructions
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee1-0/+1
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee1-0/+2
2011-03-25[opcodes] fixed up instruction tableAndrew Waterman1-207/+197
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman1-2/+3
2011-01-31[opcodes] fixed verilog generation for shiftsAndrew Waterman1-3/+3
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-23/+22
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman1-0/+1
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-59/+59
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-90/+67
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman1-125/+164
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-33/+35
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman1-6/+6
2010-10-31[opcodes] add latex table for rm stuffYunsup Lee1-60/+145
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman1-1/+41
Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
2010-10-20[opcodes] changed formatting of optab section headersAndrew Waterman1-6/+6
2010-10-05[opcodes] updated parse-opcodes for latex tablesYunsup Lee1-50/+100
2010-10-05[opcodes] update parse-opcodesYunsup Lee1-20/+20
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-38/+36
2010-09-12[opcodes] fixed tex table for ish,ishw typesYunsup Lee1-41/+38
2010-09-12[opcodes] change rsh to ish typesYunsup Lee1-9/+9
2010-09-12[opcodes] fixed verilog generation for ish,ishw typesYunsup Lee1-8/+8
2010-09-12[xcc, sim] moved shamt field and renamed shiftsAndrew Waterman1-2/+2
2010-09-12add -verilog optionYunsup Lee1-0/+111
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