| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2010-09-10 | [opcodes] latex table generation added, new opcode mapping | Yunsup Lee | 1 | -142/+500 | |
| 2010-09-06 | [sim] added atomic memory operations | Andrew Waterman | 1 | -1/+0 | |
| 2010-08-22 | [xcc,sim] added fused multiply-add and its cousins | Andrew Waterman | 1 | -0/+1 | |
| 2010-08-03 | [sim,xcc] removed sll32/srl32/sra32 opcodes | Andrew Waterman | 1 | -1/+2 | |
| These instructions handled static shift amounts >= 32. Since we have a 6-bit shift amount field, these opcodes are no longer necessary. | |||||
| 2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -89/+137 | |
| Massive changes to gcc, binutils to support new instruction encoding. Simulator reflects these changes. | |||||
| 2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+115 | |
| Moved cross-compiler to /xcc/ rather than / Added ISA sim in /sim/ Added Proxy Kernel in /pk/ (to be cleaned up) Added opcode map to /opcodes/ (ditto) Added documentation to /doc/ | |||||
 |
index : riscv-tools/riscv-opcodes.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |
path: root/parse-opcodes