Age | Commit message (Expand) | Author | Files | Lines |
2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 1 | -36/+35 |
2013-11-25 | New privileged ISA | Andrew Waterman | 1 | -15/+71 |
2013-11-22 | add missing imm for stores | Yunsup Lee | 1 | -0/+1 |
2013-10-29 | changes to the instr-table | Yunsup Lee | 1 | -14/+16 |
2013-10-10 | revamp hwacha-v3 opcodes | Yunsup Lee | 1 | -2/+1 |
2013-09-21 | Fix funct field in tables. | Andrew Waterman | 1 | -1/+1 |
2013-09-21 | Update ISA encoding | Andrew Waterman | 1 | -191/+238 |
2013-08-07 | hwacha v3: inst format follows the new rocket accelerator extensions | Yunsup Lee | 1 | -0/+2 |
2013-08-06 | Rename MTFSR/MFFSR to FSSR/FRSR | Andrew Waterman | 1 | -2/+2 |
2013-07-31 | HW ignores upper bits of fence, but SW supplies 0 | Andrew Waterman | 1 | -10/+14 |
2013-07-26 | tweaks | Yunsup Lee | 1 | -11/+13 |
2013-07-26 | Factor out Hwacha/RVC and rename MFTX/MXTF to FMV | Andrew Waterman | 1 | -4/+4 |
2013-07-25 | Refactor parse-opcodes | Andrew Waterman | 1 | -303/+84 |
2013-04-17 | add auipc, lr, sc | Andrew Waterman | 1 | -0/+1 |
2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+791 |
2011-06-19 | Renamed packages | Andrew Waterman | 1 | -791/+0 |
2011-06-19 | [riscv-isa-run] code cleanup; added README | Andrew Waterman | 1 | -3/+4 |
2011-06-10 | [sim, opcodes] made sim more decoupled from opcodes | Andrew Waterman | 1 | -59/+5 |
2011-05-29 | [sim,opcodes] improved sim build and run performance | Andrew Waterman | 1 | -46/+59 |
2011-05-18 | [opcodes,pk,sim] add more vector traps (for #banks, illegal instructions) | Yunsup Lee | 1 | -2/+2 |
2011-05-15 | [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts | Yunsup Lee | 1 | -3/+28 |
2011-04-24 | [xcc,sim,opcodes] added c.addiw | Andrew Waterman | 1 | -26/+1 |
2011-04-24 | [xcc,sim,opcodes] added more RVC instructions | Andrew Waterman | 1 | -0/+1 |
2011-04-12 | [xcc,sim] rvc loads and stores | Andrew Waterman | 1 | -0/+4 |
2011-04-11 | [xcc,sim,opcodes] more rvc instructions and bug fixes | Andrew Waterman | 1 | -1/+4 |
2011-04-09 | [xcc, sim] added rvc insn c.li; misc fixes | Andrew Waterman | 1 | -1/+5 |
2011-04-09 | [xcc,pk,sim,opcodes] added first RVC instruction | Andrew Waterman | 1 | -4/+7 |
2011-04-07 | [pk,sim] fixed parse-opcodes bug | Andrew Waterman | 1 | -2/+2 |
2011-04-05 | [opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in... | Yunsup Lee | 1 | -16/+17 |
2011-04-04 | [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.) | Yunsup Lee | 1 | -0/+1 |
2011-04-04 | [opcodes,pk,sim,xcc] add vector mem instructions | Yunsup Lee | 1 | -0/+2 |
2011-03-25 | [opcodes] fixed up instruction table | Andrew Waterman | 1 | -207/+197 |
2011-03-25 | [xcc,pk,opcodes,sim] updated encoding/insn names | Andrew Waterman | 1 | -2/+3 |
2011-01-31 | [opcodes] fixed verilog generation for shifts | Andrew Waterman | 1 | -3/+3 |
2011-01-25 | [opcodes,pk,sim,xcc] great renumbering of 2011, part deux | Andrew Waterman | 1 | -23/+22 |
2011-01-20 | [sim, pk, xcc, opcodes] great instruction renaming of 2011 | Andrew Waterman | 1 | -0/+1 |
2011-01-03 | [opcodes,pk,sim,xcc] flip fields to favor little endian | Yunsup Lee | 1 | -59/+59 |
2010-11-21 | [opcodes, pk, sim, xcc] Tweaked FP encoding | Andrew Waterman | 1 | -90/+67 |
2010-11-21 | [opcodes] generate latex and verilog correctly | Andrew Waterman | 1 | -125/+164 |
2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -33/+35 |
2010-11-21 | [opcodes, pk, sim, xcc] made jumps shorter and PC-relative | Andrew Waterman | 1 | -6/+6 |
2010-10-31 | [opcodes] add latex table for rm stuff | Yunsup Lee | 1 | -60/+145 |
2010-10-25 | [sim,xcc,pk,opcodes] static rounding modes for FP insns | Andrew Waterman | 1 | -1/+41 |
2010-10-20 | [opcodes] changed formatting of optab section headers | Andrew Waterman | 1 | -6/+6 |
2010-10-05 | [opcodes] updated parse-opcodes for latex tables | Yunsup Lee | 1 | -50/+100 |
2010-10-05 | [opcodes] update parse-opcodes | Yunsup Lee | 1 | -20/+20 |
2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -38/+36 |
2010-09-12 | [opcodes] fixed tex table for ish,ishw types | Yunsup Lee | 1 | -41/+38 |
2010-09-12 | [opcodes] change rsh to ish types | Yunsup Lee | 1 | -9/+9 |
2010-09-12 | [opcodes] fixed verilog generation for ish,ishw types | Yunsup Lee | 1 | -8/+8 |