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AgeCommit message (Expand)AuthorFilesLines
2016-04-30ERET -> xRETAndrew Waterman1-1/+1
2016-04-06Remove nonstandard stats, uarch CSRsAndrew Waterman1-21/+0
2016-03-03Update CSR encodingAndrew Waterman1-0/+19
2016-02-28WIP on priv spec v1.9Andrew Waterman1-30/+14
2016-02-28WIP on priv spec v1.9Andrew Waterman1-16/+15
2016-02-05WIP on priv spec v1.9Andrew Waterman1-5/+4
2015-11-12add miobase, mipi; drop send_ipiAndrew Waterman1-1/+2
2015-09-28In C headers, keep instructions in original input orderAndrew Waterman1-2/+2
2015-09-08Use BitPat instead of Bits for Chisel3Andrew Waterman1-1/+1
2015-09-08update to latest RVC proposalAndrew Waterman1-2/+5
2015-07-28Fix DECLARE_CAUSE macrosAndrew Waterman1-1/+1
2015-07-05New machine-mode timer facilityAndrew Waterman1-1/+1
2015-05-09Update to privileged architecture version 1.7Andrew Waterman1-25/+96
2015-03-30RVC draftAndrew Waterman1-13/+2
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman1-8/+6
2015-03-12Update to new privileged specAndrew Waterman1-27/+53
2014-04-03Move stats registerStephen Twigg1-1/+1
2014-03-18Add rdcycleh etc. for RV32Andrew Waterman1-6/+22
2014-03-11Fix syntax error in generated opcodesAndrew Waterman1-2/+2
2014-03-11New FP encodingAndrew Waterman1-15/+20
2014-03-06Add fclass.{s|d} instructionsAndrew Waterman1-2/+4
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman1-16/+16
2014-02-06Reserve 16 uarch-specific read-only userspace countersAndrew Waterman1-0/+16
2014-01-21Add DECLARE_CAUSE macroAndrew Waterman1-0/+5
2014-01-21Auto-generate exception cause numbersAndrew Waterman1-0/+27
2013-12-09New RDCYCLE encodingAndrew Waterman1-36/+35
2013-11-25New privileged ISAAndrew Waterman1-15/+71
2013-11-22add missing imm for storesYunsup Lee1-0/+1
2013-10-29changes to the instr-tableYunsup Lee1-14/+16
2013-10-10revamp hwacha-v3 opcodesYunsup Lee1-2/+1
2013-09-21Fix funct field in tables.Andrew Waterman1-1/+1
2013-09-21Update ISA encodingAndrew Waterman1-191/+238
2013-08-07hwacha v3: inst format follows the new rocket accelerator extensionsYunsup Lee1-0/+2
2013-08-06Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman1-2/+2
2013-07-31HW ignores upper bits of fence, but SW supplies 0Andrew Waterman1-10/+14
2013-07-26tweaksYunsup Lee1-11/+13
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-4/+4
2013-07-25Refactor parse-opcodesAndrew Waterman1-303/+84
2013-04-17add auipc, lr, scAndrew Waterman1-0/+1
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+791
2011-06-19Renamed packagesAndrew Waterman1-791/+0
2011-06-19[riscv-isa-run] code cleanup; added READMEAndrew Waterman1-3/+4
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-59/+5
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-46/+59
2011-05-18[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Yunsup Lee1-2/+2
2011-05-15[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsYunsup Lee1-3/+28
2011-04-24[xcc,sim,opcodes] added c.addiwAndrew Waterman1-26/+1
2011-04-24[xcc,sim,opcodes] added more RVC instructionsAndrew Waterman1-0/+1
2011-04-12[xcc,sim] rvc loads and storesAndrew Waterman1-0/+4
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-1/+4
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