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2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-2/+4
2011-04-09[xcc, sim] added rvc insn c.li; misc fixesAndrew Waterman1-1/+2
2011-04-09[xcc,pk,sim,opcodes] added first RVC instructionAndrew Waterman1-5/+6
2011-04-06[opcodes,pk,sim,xcc] fix utidx - add rdYunsup Lee1-1/+1
2011-04-05[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵Yunsup Lee1-43/+113
instructions
2011-04-04[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Yunsup Lee1-0/+6
2011-04-04[opcodes,pk,sim,xcc] add vector mem instructionsYunsup Lee1-0/+38
2011-04-04[opcodes,pk,sim,xcc] add stop,utidx instructionsYunsup Lee1-0/+2
2011-04-04[opcodes,pk,sim,xcc] add fence instructions for vector unitYunsup Lee1-2/+6
2011-03-25[opcodes] minor opcode changesAndrew Waterman1-17/+17
2011-03-25[sim,pk,xcc,opcodes] removed fminmag/fmaxmagAndrew Waterman1-4/+0
2011-03-25[xcc,pk,opcodes,sim] updated encoding/insn namesAndrew Waterman1-34/+46
2011-02-15[xcc,opcodes,pk,sim] krste's re-renaming spreeAndrew Waterman1-41/+41
2011-02-15[xcc,sim,opcodes] removed mtflh/mffl/mffhAndrew Waterman1-3/+0
in rv32 these will be replaced with loads and stores.
2011-02-02[sim,xcc,opcodes] added back mtflh.dAndrew Waterman1-1/+2
2011-02-02[opcodes,pk,sim,xcc] synci now bombs whole icacheAndrew Waterman1-1/+1
2011-02-01[xcc,opcodes,pk,sim] cleanup to FP ISAAndrew Waterman1-27/+26
- Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64
2011-01-25[sim,opcodes] add mulhsu instructionAndrew Waterman1-1/+2
2011-01-25[opcodes,pk,sim,xcc] great renumbering of 2011, part deuxAndrew Waterman1-180/+177
2011-01-20[sim, pk, xcc, opcodes] great instruction renaming of 2011Andrew Waterman1-89/+92
2011-01-18[opcodes, sim, xcc] made *w insns illegal in RV32Andrew Waterman1-2/+0
now generic variants behave differently in RV32 and RV64.
2011-01-17[opcodes, pk, sim, xcc] removed nor, normalized macros to addiAndrew Waterman1-1/+0
2011-01-03[opcodes,pk,sim,xcc] flip fields to favor little endianYunsup Lee1-182/+180
2010-11-21[opcodes, pk, sim, xcc] Tweaked FP encodingAndrew Waterman1-70/+37
2010-11-21[opcodes] generate latex and verilog correctlyAndrew Waterman1-10/+10
2010-11-21[xcc, sim, pk, opcodes] new instruction encoding!Andrew Waterman1-212/+215
2010-11-21[opcodes, pk, sim, xcc] made jumps shorter and PC-relativeAndrew Waterman1-2/+2
2010-10-31[opcodes] add latex table for rm stuffYunsup Lee1-36/+36
2010-10-25[sim,xcc,pk,opcodes] static rounding modes for FP insnsAndrew Waterman1-20/+52
Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.)
2010-10-07[xcc] modified opcodes for better FP decode mappingAndrew Waterman1-7/+7
2010-10-05[opcodes] added code field back to syscall/breakAndrew Waterman1-2/+2
2010-10-02[xcc, sim] mff now uses rs2 for dataAndrew Waterman1-43/+43
this is symmetric with fp stores, so we only need one decoding pipe
2010-09-28[opcodes, sim, xcc] added mffl.d instructionAndrew Waterman1-64/+66
...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
2010-09-20[xcc, sim] changed instruction format so imm12 subs for rs2Andrew Waterman1-172/+172
2010-09-13[xcc, sim] replaced ble/bleu with bge/bgeuAndrew Waterman1-4/+4
This will simplify control logic (since every branch has a logical inverse)
2010-09-12[sim] renamed sllv to sll (same for other shifts)Andrew Waterman1-6/+6
2010-09-12[xcc, sim] moved shamt field and renamed shiftsAndrew Waterman1-18/+18
2010-09-12[xcc, sim] branches now are next-PC-based, not PC-basedAndrew Waterman1-1/+1
2010-09-10[sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bitAndrew Waterman1-1/+1
2010-09-10[opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit)Yunsup Lee1-0/+2
2010-09-10[opcodes] latex table generation added, new opcode mappingYunsup Lee1-181/+182
2010-09-09[opcodes,sim,xcc] move opcodes for 3 source instructionsYunsup Lee1-10/+10
2010-09-09Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu"Andrew Waterman1-2/+2
This reverts commit bf5406d4df625678bc6ec20ce1d48541541dba54. We found a clever way to efficiently implement slti/sltiu despite the reversed operands. The trick is because of the following fact: (a < b) === !(b <= a) === !(b-1 < a) So just turn off the carry-in when doing the subtraction for the comparison.
2010-09-07[xcc, sim] added slei/sleui in lieu of slti/sltiuAndrew Waterman1-2/+2
Rationale was that since we have the datapath for rc = (ra < rb), it's straightforward to also add rc = !(imm < rb) = (rb <= imm).
2010-09-06[sim, xcc] bthread threading model exposed; insn encoding cleaned upAndrew Waterman1-15/+14
2010-09-06[sim] added atomic memory operationsAndrew Waterman1-5/+23
2010-08-22[xcc,sim] added fused multiply-add and its cousinsAndrew Waterman1-0/+10
2010-08-22[xcc,sim] Eliminated slori instructionAndrew Waterman1-1/+0
the "li" macro in RISC-V assembly isn't as efficient anymore for 64b constants, and "la" doesn't work for 64b addresses with ".set noat". But it's worth it to remove an ugly instruction.
2010-08-09[xcc,sim] implement FP using softfloatAndrew Waterman1-31/+30
The intersection of the Hauser FP and MIPS FP is implemented.
2010-08-05[sim,xcc] Added first few Hauser FP insns (sign-injection)Andrew Waterman1-8/+17
Also updated FPmove test case to test negation and moving between FP regs
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