Age | Commit message (Expand) | Author | Files | Lines |
2011-01-20 | [sim, pk, xcc, opcodes] great instruction renaming of 2011 | Andrew Waterman | 1 | -89/+92 |
2011-01-18 | [opcodes, sim, xcc] made *w insns illegal in RV32 | Andrew Waterman | 1 | -2/+0 |
2011-01-17 | [opcodes, pk, sim, xcc] removed nor, normalized macros to addi | Andrew Waterman | 1 | -1/+0 |
2011-01-03 | [opcodes,pk,sim,xcc] flip fields to favor little endian | Yunsup Lee | 1 | -182/+180 |
2010-11-21 | [opcodes, pk, sim, xcc] Tweaked FP encoding | Andrew Waterman | 1 | -70/+37 |
2010-11-21 | [opcodes] generate latex and verilog correctly | Andrew Waterman | 1 | -10/+10 |
2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -212/+215 |
2010-11-21 | [opcodes, pk, sim, xcc] made jumps shorter and PC-relative | Andrew Waterman | 1 | -2/+2 |
2010-10-31 | [opcodes] add latex table for rm stuff | Yunsup Lee | 1 | -36/+36 |
2010-10-25 | [sim,xcc,pk,opcodes] static rounding modes for FP insns | Andrew Waterman | 1 | -20/+52 |
2010-10-07 | [xcc] modified opcodes for better FP decode mapping | Andrew Waterman | 1 | -7/+7 |
2010-10-05 | [opcodes] added code field back to syscall/break | Andrew Waterman | 1 | -2/+2 |
2010-10-02 | [xcc, sim] mff now uses rs2 for data | Andrew Waterman | 1 | -43/+43 |
2010-09-28 | [opcodes, sim, xcc] added mffl.d instruction | Andrew Waterman | 1 | -64/+66 |
2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -172/+172 |
2010-09-13 | [xcc, sim] replaced ble/bleu with bge/bgeu | Andrew Waterman | 1 | -4/+4 |
2010-09-12 | [sim] renamed sllv to sll (same for other shifts) | Andrew Waterman | 1 | -6/+6 |
2010-09-12 | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 1 | -18/+18 |
2010-09-12 | [xcc, sim] branches now are next-PC-based, not PC-based | Andrew Waterman | 1 | -1/+1 |
2010-09-10 | [sim, xcc] Added mffh.d/mtflh.d; fixed FP ABI for 32-bit | Andrew Waterman | 1 | -1/+1 |
2010-09-10 | [opcodes,xcc,sim] mffh.d,mtfh.d added (broken commit) | Yunsup Lee | 1 | -0/+2 |
2010-09-10 | [opcodes] latex table generation added, new opcode mapping | Yunsup Lee | 1 | -181/+182 |
2010-09-09 | [opcodes,sim,xcc] move opcodes for 3 source instructions | Yunsup Lee | 1 | -10/+10 |
2010-09-09 | Revert "[xcc, sim] added slei/sleui in lieu of slti/sltiu" | Andrew Waterman | 1 | -2/+2 |
2010-09-07 | [xcc, sim] added slei/sleui in lieu of slti/sltiu | Andrew Waterman | 1 | -2/+2 |
2010-09-06 | [sim, xcc] bthread threading model exposed; insn encoding cleaned up | Andrew Waterman | 1 | -15/+14 |
2010-09-06 | [sim] added atomic memory operations | Andrew Waterman | 1 | -5/+23 |
2010-08-22 | [xcc,sim] added fused multiply-add and its cousins | Andrew Waterman | 1 | -0/+10 |
2010-08-22 | [xcc,sim] Eliminated slori instruction | Andrew Waterman | 1 | -1/+0 |
2010-08-09 | [xcc,sim] implement FP using softfloat | Andrew Waterman | 1 | -31/+30 |
2010-08-05 | [sim,xcc] Added first few Hauser FP insns (sign-injection) | Andrew Waterman | 1 | -8/+17 |
2010-08-04 | [xcc] Removed ctc1, cfc1 instructions; added fp move test case | Andrew Waterman | 1 | -2/+0 |
2010-08-04 | [xcc,pk,sim] Added first part of FP support | Andrew Waterman | 1 | -6/+4 |
2010-08-03 | [sim,xcc] removed sll32/srl32/sra32 opcodes | Andrew Waterman | 1 | -9/+6 |
2010-08-03 | [pk,sim,xcc] Renamed instructions to RISC-V spec | Andrew Waterman | 1 | -26/+26 |
2010-07-28 | [sim,xcc] Changed instruction format to RISC-V | Andrew Waterman | 1 | -147/+163 |
2010-07-18 | Reorganized directory structure | Andrew Waterman | 1 | -0/+148 |