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See https://github.com/riscv/riscv-v-spec/pull/317
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https://github.com/riscv/riscv-v-spec/pull/295
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Closes #33
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See https://github.com/riscv/riscv-v-spec/pull/247
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See https://github.com/riscv/riscv-v-spec/pull/227
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* rvv: fault-first also support segement
based on 7.8.1, add missing segment supoort for fault first load
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: comparision instructions has 'm' prefix
add 'm' prefix since the destination is mask register
ref:
https://github.com/riscv/riscv-v-spec/pull/181
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: reserved vid.v operand
follow v0.7.1 change
ref:
https://github.com/riscv/riscv-v-spec/issues/160
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: add vfrsub.vf
follow v-spec 0.7.1
ref:
https://github.com/riscv/riscv-v-spec/commit/65d2e233d4f5a95d27edf3fcd8b590b6b3deffbc
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
* rvv: add amo encoding table
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Note that vmiota is being renamed to viota:
https://github.com/riscv/riscv-v-spec/pull/180
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This is not currently stated in the spec, but there is a pull request to
make this explicit: https://github.com/riscv/riscv-v-spec/pull/179
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add most of vector instruction encoding described in v-spec 0.7.
except for 'Zvamo' extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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