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2021-02-23rvv: add vle1/vse1 instructionsChih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-12-02rvv: follow change of indexed ordered/unordered load/storeChih-Min Chao1-26/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-12-02rvv: remove quad instructionsChih-Min Chao1-5/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-09-17Add encodings of vfrsqrte7.v and vfrece7.v (#49)Zhen Wei1-0/+2
2020-08-03Make *.vv operand naming be consistent with type (#46)Zhen Wei1-48/+48
2020-07-27rvv: add eew 128 ~ 1024 load/store opcodeChih-Min Chao1-33/+65
spike doesn't implement them but the disassembler use it Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-27rvv: add whole ldst pseudo instruction and update reference linkChih-Min Chao1-1/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-21Add vrgatherei16.vvAndrew Waterman1-10/+11
https://github.com/riscv/riscv-v-spec/commit/a67925038b653a75cd7eadb68b9915449941745d
2020-07-21Incorporate whole-register load/store changes in RVV v1.0-draftAndrew Waterman1-2/+20
https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5
2020-05-12RVV v0.9: AMOs with explicit element widthsAndrew Waterman1-19/+39
https://github.com/riscv/riscv-v-spec/commit/cf03f382ab2e5cfa24874ebc7a190fb0311e3f9a
2020-05-12RVV v0.9: loads/stores with explicit element widthsAndrew Waterman1-45/+33
https://github.com/riscv/riscv-v-spec/commit/aa6032ce9ea4ef8c9f15e7dcb1fa6c7d7ac2d463
2020-05-12RVV v0.9: change vl1r/vs1r opcodesAndrew Waterman1-2/+2
https://github.com/riscv/riscv-v-spec/commit/5a0911c56394cc9ae2b5ade60a019cc82b2f926a
2020-05-12RVV v0.9: new extension instructionsAndrew Waterman1-0/+9
https://github.com/riscv/riscv-v-spec/commit/b6c85cdad7c120780c2b6241b316567740c9affe#diff-34bccafef6cfe01367796362310416df
2020-05-12RVV v0.9: move VFUNARY0/VFUNARY1 opcodesAndrew Waterman1-26/+26
https://github.com/riscv/riscv-v-spec/commit/159124d3da6d1fe693bffc6080ff69876aa66c43#diff-34bccafef6cfe01367796362310416df
2020-03-28Add FP->int truncating conversionsAndrew Waterman1-17/+23
See https://github.com/riscv/riscv-v-spec/pull/403/
2020-03-28Add vfslide1up/downAndrew Waterman1-8/+10
See https://github.com/riscv/riscv-v-spec/pull/402/
2019-11-28Remove vamo*q; replace vamo*d with vamo*eAndrew Waterman1-19/+9
2019-11-28Add vmv<nf>r.vAndrew Waterman1-0/+4
2019-11-28rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wiChih-Min Chao1-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28rvv: add load/store whole registerChih-Min Chao1-2/+7
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28rvv: replace vfncvt suffix with .wChih-Min Chao1-6/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28rvv: add vqmacc variant insnChih-Min Chao1-0/+9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-15Remove scaled fixed-point multiply-add instructionsAndrew Waterman1-8/+0
See https://github.com/riscv/riscv-v-spec/commit/063b128bd91390c64796fe1e1546a8855fdbaf35
2019-11-15vcompress is encoded with vm=1Andrew Waterman1-1/+1
See https://github.com/riscv/riscv-v-spec/commit/da9ae36997183141521d3f850a935c99535ae73b
2019-11-15Add vaaddu/vasubu; change vaadd/vasub opcodesAndrew Waterman1-5/+10
See https://github.com/riscv/riscv-v-spec/commit/c2f3157e34d3a0f77ccbbc502bdf1530da17aba8
2019-11-11Update encoding of vadc and friendsAndrew Waterman1-10/+10
See https://github.com/riscv/riscv-v-spec/pull/317
2019-11-11Add vfncvt.rod.f.f.v instructionAndrew Waterman1-5/+6
2019-09-17vwmaccsu/us opcodes have been swappedAndrew Waterman1-6/+6
https://github.com/riscv/riscv-v-spec/pull/295
2019-08-26More updates to rvv encodingAndrew Waterman1-13/+11
Closes #33
2019-07-15vext.x.v -> vmv.x.sAndrew Waterman1-1/+1
See https://github.com/riscv/riscv-v-spec/pull/247
2019-07-05Fix encoding of vfclass.v instructionAndrew Waterman1-1/+1
2019-06-28vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcodeAndrew Waterman1-2/+2
See https://github.com/riscv/riscv-v-spec/pull/227
2019-06-18v-spec 0.7.1-0607 (#29)Chih-Min Chao1-41/+73
* rvv: fault-first also support segement based on 7.8.1, add missing segment supoort for fault first load Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: comparision instructions has 'm' prefix add 'm' prefix since the destination is mask register ref: https://github.com/riscv/riscv-v-spec/pull/181 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: reserved vid.v operand follow v0.7.1 change ref: https://github.com/riscv/riscv-v-spec/issues/160 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add vfrsub.vf follow v-spec 0.7.1 ref: https://github.com/riscv/riscv-v-spec/commit/65d2e233d4f5a95d27edf3fcd8b590b6b3deffbc Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add amo encoding table Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-11Expand vfunary0 and vfunary1 opcodes into sub-instructionsAndrew Waterman1-2/+20
2019-06-05More V 0.7.1 updatesAndrew Waterman1-12/+10
2019-06-05Some V 0.7.1 updatesAndrew Waterman1-9/+18
2019-06-05VMV.S.X requires vs2=0Andrew Waterman1-2/+2
2019-05-17Expand vmunary0 into its constituent instructionsAndrew Waterman1-1/+6
Note that vmiota is being renamed to viota: https://github.com/riscv/riscv-v-spec/pull/180
2019-05-17vmv/vext/vfmv are reserved when vm=0Andrew Waterman1-4/+4
This is not currently stated in the spec, but there is a pull request to make this explicit: https://github.com/riscv/riscv-v-spec/pull/179
2019-05-17vadc/vsbc require vm=1Andrew Waterman1-5/+5
2019-05-16rvv: vector instruction encodingChih-Min Chao1-0/+378
add most of vector instruction encoding described in v-spec 0.7. except for 'Zvamo' extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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