Age | Commit message (Expand) | Author | Files | Lines |
2010-11-21 | [opcodes, pk, sim, xcc] Tweaked FP encoding | Andrew Waterman | 1 | -59/+34 |
2010-11-21 | [opcodes] generate latex and verilog correctly | Andrew Waterman | 1 | -175/+175 |
2010-11-21 | [xcc, sim, pk, opcodes] new instruction encoding! | Andrew Waterman | 1 | -165/+164 |
2010-11-21 | [opcodes, pk, sim, xcc] made jumps shorter and PC-relative | Andrew Waterman | 1 | -2/+2 |
2010-10-25 | [sim,xcc,pk,opcodes] static rounding modes for FP insns | Andrew Waterman | 1 | -18/+43 |
2010-10-15 | [pk, sim] added FPU emulation support to proxy kernel | Andrew Waterman | 1 | -1/+1 |
2010-10-07 | [xcc] modified opcodes for better FP decode mapping | Andrew Waterman | 1 | -7/+7 |
2010-10-05 | [opcodes] updated parse-opcodes for latex tables | Yunsup Lee | 1 | -12/+12 |
2010-10-05 | [opcodes] update parse-opcodes | Yunsup Lee | 1 | -2/+2 |
2010-10-02 | [xcc, sim] mff now uses rs2 for data | Andrew Waterman | 1 | -29/+29 |
2010-09-28 | [opcodes, sim, xcc] added mffl.d instruction | Andrew Waterman | 1 | -54/+55 |
2010-09-20 | [xcc, sim] changed instruction format so imm12 subs for rs2 | Andrew Waterman | 1 | -42/+42 |
2010-09-13 | [xcc, sim] replaced ble/bleu with bge/bgeu | Andrew Waterman | 1 | -4/+4 |
2010-09-12 | [opcodes] fixed tex table for ish,ishw types | Yunsup Lee | 1 | -6/+6 |
2010-09-12 | [opcodes] fixed verilog generation for ish,ishw types | Yunsup Lee | 1 | -6/+6 |
2010-09-12 | [sim] renamed sllv to sll (same for other shifts) | Andrew Waterman | 1 | -6/+6 |
2010-09-12 | [xcc, sim] moved shamt field and renamed shifts | Andrew Waterman | 1 | -17/+17 |
2010-09-12 | [xcc, sim] branches now are next-PC-based, not PC-based | Andrew Waterman | 1 | -1/+1 |
2010-09-12 | add -verilog option | Yunsup Lee | 1 | -0/+153 |