| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2016-06-08 | Add breakpoint CSRs | Andrew Waterman | 1 | -0/+10 |
| 2016-06-03 | Keep DCSR_XDEBUGVER unsigned. | Tim Newsome | 1 | -1/+1 |
| 2016-06-01 | Add dret instruction and debug CSRs. (#5) | Tim Newsome | 1 | -0/+23 |
| 2016-05-13 | Rename "Device Interrupt" to "External Interrupt" | Andrew Waterman | 1 | -3/+6 |
| 2016-04-30 | Remove mcfgaddr; change memory map | Andrew Waterman | 1 | -3/+6 |
| 2016-03-10 | Allow immediates for write_csr; check for signedness | Andrew Waterman | 1 | -6/+12 |
| 2016-03-03 | Update CSR encoding | Andrew Waterman | 1 | -2/+5 |
| 2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -5/+6 |
| 2016-02-05 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -33/+37 |
| 2015-05-14 | Fix VM, MIP encoding | Andrew Waterman | 1 | -6/+6 |
| 2015-05-09 | Update to privileged architecture version 1.7 | Andrew Waterman | 1 | -72/+70 |
| 2015-04-02 | Distinguish Sv39/Sv48; reserve some PPN bits | Andrew Waterman | 1 | -4/+6 |
| 2015-03-24 | New virtual memory implementation (Sv39) | Andrew Waterman | 1 | -17/+38 |
| 2015-03-12 | Add referenced/dirty bits to PTE | Andrew Waterman | 1 | -0/+2 |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -32/+71 |
| 2014-02-06 | Reserve 16 uarch-specific read-only userspace counters | Andrew Waterman | 1 | -0/+8 |
| 2014-01-21 | Auto-generate exception cause numbers | Andrew Waterman | 1 | -13/+0 |
| 2013-11-25 | New privileged ISA | Andrew Waterman | 1 | -0/+101 |
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index : riscv-tools/riscv-opcodes.git | |
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path: root/encoding.h