Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2021-07-19 | Virtual memory updates (#76) | Daniel Lustig | 1 | -0/+3 | |
* Add Svinval instructions * Add PTE defines for Priv 1.12 and Svpbmt | |||||
2021-06-07 | Update PTE_N encoding | Andrew Waterman | 1 | -1/+1 | |
See https://github.com/riscv/riscv-isa-sim/pull/724 | |||||
2021-01-23 | Removing platform-specific definitions (#59) | Dan Petrisko | 1 | -6/+0 | |
2021-01-08 | Add Zsn to encoding.h | Andrew Waterman | 1 | -0/+1 | |
2021-01-08 | Update mstatus/sstatus fields for hypervisor v0.6 | Andrew Waterman | 1 | -2/+8 | |
2020-07-31 | hyperviosr: add csr mask and interrupt macro name | Chih-Min Chao | 1 | -7/+46 | |
This part copy the implementation which has been merged in spike Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-05-04 | Add DCSR_CAUSE_GROUP. (#44) | Tim Newsome | 1 | -0/+1 | |
2020-02-24 | Add N-extension CSRs and status bits. (#37) | michael-roe | 1 | -0/+9 | |
2020-02-13 | Remove mstatus.HPP; move mstatus.VS to its old location | Andrew Waterman | 1 | -3/+2 | |
See https://github.com/riscv/riscv-v-spec/pull/351 | |||||
2019-11-28 | rvv: add vleb csr register and mstatus.vs field | Chih-Min Chao | 1 | -0/+2 | |
1. vleb is read-only CSR to keep vector implementation lenght in byte 2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2017-12-27 | Use old C style comments. (#18) | Tim Newsome | 1 | -11/+11 | |
This improves the chance we can use this file with older, pickier compilers. Also it makes the OpenOCD patch check script happier. | |||||
2017-11-27 | Rename sptbr to satp and sbadaddr to stval | Andrew Waterman | 1 | -15/+15 | |
Closes #17 | |||||
2017-05-07 | Add UXl/SXL | Andrew Waterman | 1 | -0/+3 | |
2017-03-30 | New PMP encoding | Andrew Waterman | 1 | -5/+6 | |
2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 1 | -3/+2 | |
2017-03-23 | Add PMP | Andrew Waterman | 1 | -1/+12 | |
2017-03-23 | Add TW/TVM/TSR fields to mstatus | Andrew Waterman | 1 | -1/+4 | |
2017-03-09 | Update SPTBR fields | Andrew Waterman | 1 | -14/+9 | |
2017-02-20 | Use gcc csr register constraint | Andrew Waterman | 1 | -16/+4 | |
2017-02-20 | Drop mstatus.VM field | Andrew Waterman | 1 | -1/+0 | |
2017-02-08 | Encode VM type in sptbr, not mstatus | Andrew Waterman | 1 | -0/+14 | |
https://github.com/riscv/riscv-isa-manual/issues/4 | |||||
2016-12-06 | avoid non-standard predefined macros | Andrew Waterman | 1 | -1/+1 | |
2016-08-26 | Add mcontrol type constants. (#11) | Tim Newsome | 1 | -0/+3 | |
2016-08-25 | Make hardware triggers match latest spec. | Tim Newsome | 1 | -18/+30 | |
2016-07-06 | Update to new PTE format | Andrew Waterman | 1 | -33/+10 | |
2016-06-09 | Update breakpoint spec | Andrew Waterman | 1 | -8/+15 | |
2016-06-08 | Add breakpoint CSRs | Andrew Waterman | 1 | -0/+10 | |
2016-06-03 | Keep DCSR_XDEBUGVER unsigned. | Tim Newsome | 1 | -1/+1 | |
2016-06-01 | Add dret instruction and debug CSRs. (#5) | Tim Newsome | 1 | -0/+23 | |
2016-05-13 | Rename "Device Interrupt" to "External Interrupt" | Andrew Waterman | 1 | -3/+6 | |
2016-04-30 | Remove mcfgaddr; change memory map | Andrew Waterman | 1 | -3/+6 | |
2016-03-10 | Allow immediates for write_csr; check for signedness | Andrew Waterman | 1 | -6/+12 | |
2016-03-03 | Update CSR encoding | Andrew Waterman | 1 | -2/+5 | |
2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -5/+6 | |
2016-02-05 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -33/+37 | |
2015-05-14 | Fix VM, MIP encoding | Andrew Waterman | 1 | -6/+6 | |
2015-05-09 | Update to privileged architecture version 1.7 | Andrew Waterman | 1 | -72/+70 | |
2015-04-02 | Distinguish Sv39/Sv48; reserve some PPN bits | Andrew Waterman | 1 | -4/+6 | |
2015-03-24 | New virtual memory implementation (Sv39) | Andrew Waterman | 1 | -17/+38 | |
2015-03-12 | Add referenced/dirty bits to PTE | Andrew Waterman | 1 | -0/+2 | |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -32/+71 | |
2014-02-06 | Reserve 16 uarch-specific read-only userspace counters | Andrew Waterman | 1 | -0/+8 | |
2014-01-21 | Auto-generate exception cause numbers | Andrew Waterman | 1 | -13/+0 | |
2013-11-25 | New privileged ISA | Andrew Waterman | 1 | -0/+101 | |