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2015-03-12Update to new privileged specAndrew Waterman1-2/+3
2014-12-14update location of headers for new ABI/toolchainColin Schmidt1-2/+2
2014-11-22Revert "Enable the four custom instructions"Yunsup Lee1-1/+1
This reverts commit 70b52dd5fa74b5968a20ded22df4ae3a9a76d7f4. Refactoring support for custom instructions.
2014-10-24Merge branch 'pr/1'Yunsup Lee1-1/+1
Conflicts: Makefile
2014-10-23Prevent regenerating the Hwacha spike header by defaultAlbert Ou1-8/+7
Not every instruction in the main opcodes file is implemented by Hwacha; at present, updating opcodes_hwacha_ut.h requires manual culling of the unneeded instructions to avoid breaking the spike build.
2014-10-23Enable the four custom instructionsArun Thomas1-1/+1
Will update encoding.h in the following components: * riscv-isa-sim * riscv-pk * riscv-test-env
2014-04-03Add hwacha spike header file targetStephen Twigg1-1/+10
2014-01-20Merge branch 'confprec'Quan Nguyen1-1/+1
Conflicts: Makefile
2013-11-25New privileged ISAAndrew Waterman1-21/+14
2013-11-24Merge branch 'master' into confprecQuan Nguyen1-2/+2
Conflicts: Makefile
2013-11-24Add line in Makefile to parse confprecQuan Nguyen1-0/+1
2013-11-21fix slli/slliw encoding bugYunsup Lee1-1/+2
2013-10-27Move half-precision opcodes to opcodes-hwacha-utQuan Nguyen1-1/+2
2013-10-17Add half-precision floating-point instructionsQuan Nguyen1-2/+3
* Add opcodes-hwacha-pseudo to be produced as well, or else GCC will complain.
2013-09-21Update ISA encodingAndrew Waterman1-4/+5
2013-08-06Add custom opcode spaceAndrew Waterman1-1/+2
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-1/+3
2013-04-17add auipc, lr, scAndrew Waterman1-2/+6
2012-03-18change vector fence names/encodingAndrew Waterman1-0/+0
2012-03-03new instructions to handle vector exceptionsYunsup Lee1-2/+2
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+22
2011-06-19Renamed packagesAndrew Waterman1-22/+0
2011-06-19[riscv-isa-run] code cleanup; added READMEAndrew Waterman1-0/+22