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2021-07-28RVP: v0.5.2 supportChun-Ping Chung1-1/+1
2021-07-19Virtual memory updates (#76)Daniel Lustig1-1/+1
* Add Svinval instructions * Add PTE defines for Priv 1.12 and Svpbmt
2021-02-19scalar-crypto: Add opcodes for RV32K, RV64KBen Marshall1-1/+1
- Adds opcodes for RV32 and RV64 scalar crypto. - opcodes-rvk contains encodings which are for RV32 and RV64 base ISAs - opcodes-rv32/64k contains encodings which are for RV32 or RV64 - parse_opcodes has been modified: - Wnable instructions to be listed as either RV32 or RV64 only, allowing these opcodes to overlap. - The C backend has been modifed to emit the "DECLARE_RV32_ONLY" or "DECLARE_RV64_ONLY" macros as needed. - The other backends have not been modified, and may need to be in the future. On branch scalar-crypto Changes to be committed: modified: Makefile new file: opcodes-rv32k new file: opcodes-rv64k new file: opcodes-rvk modified: parse_opcodes
2021-01-08Add Zfh encodingAndrew Waterman1-1/+1
2020-11-13Merge branch 'riscv-bitmanip'Andrew Waterman1-1/+1
2020-11-08Support generating Rust code (#52)Ngo Iok Ui (Wu Yu Wei)1-0/+3
2020-08-21Add header to .h files. (#48)Tim Newsome1-1/+6
The header explains where the file came from.
2020-07-31hyperviosr: add csr mask and interrupt macro nameChih-Min Chao1-1/+1
This part copy the implementation which has been merged in spike Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-06-10Rebase d242e1ed7 onto masterAndrew Waterman1-1/+1
2020-04-07Remove RV128 for now, because it is quite speculativeAndrew Waterman1-2/+2
2020-03-03Factor out RVC opcodes into per-extension filesAndrew Waterman1-3/+3
2020-03-03Factor out opcodes into per-extension filesAndrew Waterman1-2/+2
2020-03-03Clean up MakefileAndrew Waterman1-9/+12
2019-09-12fesvr no longer needs encoding.hAndrew Waterman1-3/+2
2019-08-03(Partially) fix #30 (#31)Tommy Thorn1-12/+12
* (Partially) fix #30 With this change (and a renamed parse-opcodes) it's possible to as a Python module without having to patch the repo. Example: from parse_opcodes import parse_inputs if __name__ == "__main__": (namelist, pseudos, mask, match, arguments) = parse_inputs(["opcodes", "opcodes-rvc"]) * Fix #30: Rename parse-opcode to parse_opcode to enable module use
2019-06-19Remove redundant entry from MakefileAndrew Waterman1-1/+1
2019-06-18Add pseudos for RV32 shifts with correct immediate constraintAndrew Waterman1-1/+1
2019-05-17Add pseudos for masked/unmasked vmerge to help with decodingAndrew Waterman1-2/+2
2019-05-16rvv: vector instruction encodingChih-Min Chao1-2/+2
add most of vector instruction encoding described in v-spec 0.7. except for 'Zvamo' extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-04-23Updated path to FESVR_H in Makefile (#25)Torbjørn1-1/+1
2019-02-11Add SystemVerilog generation (#24)Florian Zaruba1-0/+3
2018-09-10Include RVC pseudos in chisel decoderAndrew Waterman1-1/+1
2017-11-27Don't copy encoding.h to binutils anymoreAndrew Waterman1-4/+0
Now that binutils is upstream, we maintain that file manually.
2017-11-27Generate encoding.h for OpenOCD as well. (#16)Tim Newsome1-2/+3
2017-05-17Merge remote-tracking branch 'origin/priv-1.10'Palmer Dabbelt1-1/+1
2017-03-31Support generating Go code (#3)Benjamin Barenblat1-0/+3
* Support generating Go code Generate Go code for the RISC-V Go port <https://github.com/riscv/riscv-go>. * Clarify use of yank in Go backend * Go: Also generate funct3, csr, and funct7 encodings * Go: Emit all instructions Changes to the RISC-V Go implementation obviate the need for GO_UNUSED_INSTRUCTIONS. * Go: Print CSRs as signed values * Go: Update parse-opcodes to use obj.As See https://github.com/golang/go/commit/0d9258a830c585. * Go: Return errors out of band * Go: Return 'ok' status instead of 'err' status Also clean up imports. * Go: Make gofmt-clean * Go: Return rs2 value for each instructions Some binary floating-point instructions (ab)use the rs2 value to hold additional instruction data, so we need that data in the Go assembler.
2017-02-14Don't update binutils' riscv-opc.h automatically anymoreAndrew Waterman1-1/+1
It's upstreamed, so avoid the false impression it can easily change.
2016-06-01Update path to binutilsAndrew Waterman1-1/+1
2016-03-10Reflect new location of encoding.h in riscv-pkAndrew Waterman1-1/+1
2016-01-13remove hwachaV3 definitionsColin Schmidt1-7/+1
2015-11-06Revert "Revert "Enable the four custom instructions""Andrew Waterman1-1/+1
This reverts commit fe5742618c1732be6000cccfbed3432596dea9e4.
2015-09-28Include pseudo-ops in inst.chiselAndrew Waterman1-2/+2
2015-09-08No need to provide GCC with encoding.h anymoreAndrew Waterman1-2/+1
2015-09-08update to latest RVC proposalAndrew Waterman1-2/+2
2015-05-31RVC v1.7 encodingAndrew Waterman1-1/+1
2015-05-09Update to privileged architecture version 1.7Andrew Waterman1-1/+4
2015-04-02Distinguish Sv39/Sv48; reserve some PPN bitsAndrew Waterman1-1/+1
2015-03-30RVC draftAndrew Waterman1-1/+1
2015-03-12Update to new privileged specAndrew Waterman1-2/+3
2014-12-14update location of headers for new ABI/toolchainColin Schmidt1-2/+2
2014-11-22Revert "Enable the four custom instructions"Yunsup Lee1-1/+1
This reverts commit 70b52dd5fa74b5968a20ded22df4ae3a9a76d7f4. Refactoring support for custom instructions.
2014-10-24Merge branch 'pr/1'Yunsup Lee1-1/+1
Conflicts: Makefile
2014-10-23Prevent regenerating the Hwacha spike header by defaultAlbert Ou1-8/+7
Not every instruction in the main opcodes file is implemented by Hwacha; at present, updating opcodes_hwacha_ut.h requires manual culling of the unneeded instructions to avoid breaking the spike build.
2014-10-23Enable the four custom instructionsArun Thomas1-1/+1
Will update encoding.h in the following components: * riscv-isa-sim * riscv-pk * riscv-test-env
2014-04-03Add hwacha spike header file targetStephen Twigg1-1/+10
2014-01-20Merge branch 'confprec'Quan Nguyen1-1/+1
Conflicts: Makefile
2013-11-25New privileged ISAAndrew Waterman1-21/+14
2013-11-24Merge branch 'master' into confprecQuan Nguyen1-2/+2
Conflicts: Makefile
2013-11-24Add line in Makefile to parse confprecQuan Nguyen1-0/+1
2013-11-21fix slli/slliw encoding bugYunsup Lee1-1/+2
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