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AgeCommit message (Expand)AuthorFilesLines
2020-06-10Rebase d242e1ed7 onto masterAndrew Waterman1-1/+1
2020-04-07Remove RV128 for now, because it is quite speculativeAndrew Waterman1-2/+2
2020-03-03Factor out RVC opcodes into per-extension filesAndrew Waterman1-3/+3
2020-03-03Factor out opcodes into per-extension filesAndrew Waterman1-2/+2
2020-03-03Clean up MakefileAndrew Waterman1-9/+12
2019-09-12fesvr no longer needs encoding.hAndrew Waterman1-3/+2
2019-08-03(Partially) fix #30 (#31)Tommy Thorn1-12/+12
2019-06-19Remove redundant entry from MakefileAndrew Waterman1-1/+1
2019-06-18Add pseudos for RV32 shifts with correct immediate constraintAndrew Waterman1-1/+1
2019-05-17Add pseudos for masked/unmasked vmerge to help with decodingAndrew Waterman1-2/+2
2019-05-16rvv: vector instruction encodingChih-Min Chao1-2/+2
2019-04-23Updated path to FESVR_H in Makefile (#25)Torbjørn1-1/+1
2019-02-11Add SystemVerilog generation (#24)Florian Zaruba1-0/+3
2018-09-10Include RVC pseudos in chisel decoderAndrew Waterman1-1/+1
2017-11-27Don't copy encoding.h to binutils anymoreAndrew Waterman1-4/+0
2017-11-27Generate encoding.h for OpenOCD as well. (#16)Tim Newsome1-2/+3
2017-05-17Merge remote-tracking branch 'origin/priv-1.10'Palmer Dabbelt1-1/+1
2017-03-31Support generating Go code (#3)Benjamin Barenblat1-0/+3
2017-02-14Don't update binutils' riscv-opc.h automatically anymoreAndrew Waterman1-1/+1
2016-06-01Update path to binutilsAndrew Waterman1-1/+1
2016-03-10Reflect new location of encoding.h in riscv-pkAndrew Waterman1-1/+1
2016-01-13remove hwachaV3 definitionsColin Schmidt1-7/+1
2015-11-06Revert "Revert "Enable the four custom instructions""Andrew Waterman1-1/+1
2015-09-28Include pseudo-ops in inst.chiselAndrew Waterman1-2/+2
2015-09-08No need to provide GCC with encoding.h anymoreAndrew Waterman1-2/+1
2015-09-08update to latest RVC proposalAndrew Waterman1-2/+2
2015-05-31RVC v1.7 encodingAndrew Waterman1-1/+1
2015-05-09Update to privileged architecture version 1.7Andrew Waterman1-1/+4
2015-04-02Distinguish Sv39/Sv48; reserve some PPN bitsAndrew Waterman1-1/+1
2015-03-30RVC draftAndrew Waterman1-1/+1
2015-03-12Update to new privileged specAndrew Waterman1-2/+3
2014-12-14update location of headers for new ABI/toolchainColin Schmidt1-2/+2
2014-11-22Revert "Enable the four custom instructions"Yunsup Lee1-1/+1
2014-10-24Merge branch 'pr/1'Yunsup Lee1-1/+1
2014-10-23Prevent regenerating the Hwacha spike header by defaultAlbert Ou1-8/+7
2014-10-23Enable the four custom instructionsArun Thomas1-1/+1
2014-04-03Add hwacha spike header file targetStephen Twigg1-1/+10
2014-01-20Merge branch 'confprec'Quan Nguyen1-1/+1
2013-11-25New privileged ISAAndrew Waterman1-21/+14
2013-11-24Merge branch 'master' into confprecQuan Nguyen1-2/+2
2013-11-24Add line in Makefile to parse confprecQuan Nguyen1-0/+1
2013-11-21fix slli/slliw encoding bugYunsup Lee1-1/+2
2013-10-27Move half-precision opcodes to opcodes-hwacha-utQuan Nguyen1-1/+2
2013-10-17Add half-precision floating-point instructionsQuan Nguyen1-2/+3
2013-09-21Update ISA encodingAndrew Waterman1-4/+5
2013-08-06Add custom opcode spaceAndrew Waterman1-1/+2
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman1-1/+3
2013-04-17add auipc, lr, scAndrew Waterman1-2/+6
2012-03-18change vector fence names/encodingAndrew Waterman1-0/+0
2012-03-03new instructions to handle vector exceptionsYunsup Lee1-2/+2
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