Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2023-11-27 | Merge pull request #211 from ved-rivos/zicfiss_insts | Andrew Waterman | 3 | -0/+26 | |
Add unratified Zicfiss extension instructions | |||||
2023-11-27 | CSR fields introduced by Zicfilp (#210) | Ved Shanbhogue | 1 | -0/+8 | |
2023-11-25 | add software check and hardware error faults | Ved Shanbhogue | 1 | -0/+2 | |
2023-11-25 | add zicfiss instructions | Ved Shanbhogue | 1 | -0/+14 | |
2023-11-25 | add compressed zicfiss instructions | Ved Shanbhogue | 1 | -0/+5 | |
2023-11-25 | add pseudoops for zicfiss insts | Ved Shanbhogue | 1 | -0/+7 | |
2023-11-24 | Merge pull request #209 from ved-rivos/zicfiss | Andrew Waterman | 2 | -0/+4 | |
Add CSR fields and SSP CSR introduced by unratified Zicfiss extension | |||||
2023-11-24 | SSP CSR introduced by Zicfiss | Ved Shanbhogue | 1 | -0/+1 | |
2023-11-24 | CSR fields introduced by Zicfiss | Ved Shanbhogue | 1 | -0/+3 | |
2023-11-01 | Merge pull request #206 from ved-rivos/zabha | Andrew Waterman | 1 | -0/+23 | |
Add unratified Zabha extension | |||||
2023-10-29 | Add Zabha AMO inst code points | Ved Shanbhogue | 1 | -0/+23 | |
2023-10-26 | Merge pull request #205 from tomhepworth/master | Andrew Waterman | 1 | -1/+3 | |
Clarified syntax of regular instructions | |||||
2023-10-26 | Clarified syntax of regular instructions | Thomas Hepworth | 1 | -1/+3 | |
See https://github.com/riscv/riscv-opcodes/issues/204 Before this change the text implied that bit encodings and variable arguments could not be mixed in the list of instruction arguments. Signed-off-by: Thomas Hepworth <tomhepworth@hotmail.co.uk> | |||||
2023-10-20 | Merge pull request #201 from mehnadnerd/master | Andrew Waterman | 1 | -0/+8 | |
Adding Zalasr | |||||
2023-10-19 | Making explicit that the aq bit is set for load-acquire, rl bit is set for ↵ | brs | 1 | -8/+8 | |
store-releasee | |||||
2023-10-18 | Changing it so Zalasr has one bit hardcoded for each, to reduce opcode ↵ | brs | 1 | -8/+8 | |
confusion hopefully | |||||
2023-10-18 | Adding load-acquire/store-release. Note they are written here as `lb.` for ↵ | brs | 1 | -0/+8 | |
the load-acquire byte (so `lb.aq` and `lb.aqrl`), I'm not sure that will work but it passes the tests here. | |||||
2023-10-17 | Add pseudo-instructions for Zimop/Zcmop (#194) | Ved Shanbhogue | 3 | -51/+114 | |
* add mop.r.N and mop.rr.N pseudo-inst * add c.mop.N pseudo-inst * add arg_lut entries and emitted pseudoops for Zimop/Zcmop * add pseudoinsts for Zimop * add pseudoinsts for Zcmop * update zcmop mnemonics * update zcmop mnemonics | |||||
2023-10-17 | Merge pull request #202 from a4lg/remove-zvamo | Andrew Waterman | 1 | -41/+0 | |
Remove unratified `Zvamo` instructions from `rv_v` | |||||
2023-10-16 | Remove unratified 'Zvamo' instructions from rv_v | Tsukasa OI | 1 | -41/+0 | |
If this is the only thing happening, I would have just moved those instructions to unratified/rv_zvamo. The reason I didn't is, there is the 'Zabha' extension (containing subword AMO instructions) in the fast track and 8-bit vector AMO instructions conflict with it. | |||||
2023-10-09 | Merge pull request #200 from felixhauptmann/master | Andrew Waterman | 2 | -131/+131 | |
Fix artifact generation | |||||
2023-10-10 | fix csv parsing | Felix Hauptmann | 2 | -131/+131 | |
2023-09-28 | Merge pull request #198 from sequencer/sdext | Neel Gala | 1 | -0/+0 | |
rename rv_debug to rv_sdext | |||||
2023-09-28 | rename rv_debug to rv_sdext | Jiuyang Liu | 1 | -0/+0 | |
2023-09-27 | Merge pull request #197 from sequencer/split_debug | Andrew Waterman | 2 | -1/+2 | |
split dret from rv_system to rv_debug | |||||
2023-09-27 | split dret from rv_system to rv_debug | Jiuyang Liu | 2 | -1/+2 | |
Because neither priv and unpriv isa mentions dret, and debug is lived in a standalone spec, move dret out from rv_system, while putting it into rv_debug | |||||
2023-09-26 | Merge pull request #195 from sequencer/constant_csv | Andrew Waterman | 5 | -611/+590 | |
split arg_lut, causes, csr, csr32 from constants.py | |||||
2023-09-25 | split arg_lut, causes, csr, csr32 from constants.py | Jiuyang Liu | 5 | -611/+590 | |
2023-09-24 | Merge pull request #196 from sequencer/patch-1 | Andrew Waterman | 1 | -1/+0 | |
Remove duplicate zimm | |||||
2023-09-25 | Remove duplicate zimm | Jiuyang Liu | 1 | -1/+0 | |
Signed-off-by: Jiuyang Liu <liu@jiuyang.me> | |||||
2023-09-23 | Merge pull request #193 from riscv/fix-changes-in-189 | Neel Gala | 1 | -0/+3 | |
retain the original shift instructions as pseudo-ops as well | |||||
2023-09-20 | retain the original shift instructions as pseudo-ops as well | Neel Gala | 1 | -0/+3 | |
This is how its done in rv32_i as well. | |||||
2023-09-19 | Merge pull request #192 from sequencer/fix_dup | Andrew Waterman | 1 | -5/+5 | |
fix instruction duplication between rv128_c and rv64_c | |||||
2023-09-20 | fix instruction duplication between rv128_c and rv64_c | Jiuyang Liu | 1 | -5/+5 | |
2023-09-16 | Merge pull request #189 from charlie-rivos/support_rv32_shift | Andrew Waterman | 1 | -3/+3 | |
Generate compressed shift instructions for rv32 | |||||
2023-09-16 | Merge pull request #188 from charlie-rivos/fix_c_addiw | Andrew Waterman | 2 | -7/+4 | |
C.ADDIW cannot have an rd of 0 | |||||
2023-09-15 | Generate compressed shift instructions for rv32 | Charlie Jenkins | 1 | -3/+3 | |
The non-compressed shift instructions have _rv32 versions. Do the same for the compressed shift instructions. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> | |||||
2023-09-15 | C.ADDIW cannot have an rd of 0 | Charlie Jenkins | 2 | -7/+4 | |
The code point of rd=0 in C.ADDIW is restricted. Fix formatting while in these files. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> | |||||
2023-09-15 | Merge pull request #187 from ved-rivos/zimop | Andrew Waterman | 2 | -0/+62 | |
Add unratified Zimop and Zcmop extension instructions | |||||
2023-09-15 | add unratified Zcmop instructions | Ved Shanbhogue | 1 | -0/+13 | |
2023-09-15 | add unratified Zimop instructions | Ved Shanbhogue | 1 | -0/+49 | |
2023-08-13 | Merge pull request #186 from ved-rivos/svadu1 | Andrew Waterman | 1 | -4/+4 | |
Svadu: Rename HADE to ADUE in *envcfg | |||||
2023-08-13 | Svadu: Rename HADE to ADUE | Ved Shanbhogue | 1 | -4/+4 | |
2023-07-31 | rv64_q_zfa: rs2 is variable field. | Nikola Rajovic | 1 | -1/+1 | |
2023-07-31 | rv32_d_zfa: rs2 is variable field. | Nikola Rajovic | 1 | -1/+1 | |
2023-07-25 | Merge pull request #181 from rivosinc/add_smcntrpmf_csrs | Andrew Waterman | 1 | -0/+4 | |
Add Smcntrpmf CSRs | |||||
2023-07-25 | Merge pull request #182 from ↵ | Andrew Waterman | 1 | -8/+8 | |
nrajovic/fix_vector_mask_register_logical_instructions rv_v: fix for Vector Mask-Register Logical instructions. | |||||
2023-07-25 | rv_v: fix for Vector Mask-Register Logical instructions. | Nikola Rajovic | 1 | -8/+8 | |
- resolves issue #180 | |||||
2023-07-24 | Add Smcntrpmf CSRs | Atul Khare | 1 | -0/+4 | |
Adds mcyclecfg (0x321), minstrefcfg (0x322), mcyclecfgh (0x721), minstretcfgh (0x722). | |||||
2023-07-12 | Merge branch 'rivosinc-smdeleg_definitions' | Andrew Waterman | 2 | -0/+14 | |