Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2016-06-08 | Add breakpoint CSRs | Andrew Waterman | 2 | -0/+14 | |
2016-06-03 | Keep DCSR_XDEBUGVER unsigned. | Tim Newsome | 1 | -1/+1 | |
2016-06-01 | Update path to binutils | Andrew Waterman | 1 | -1/+1 | |
2016-06-01 | Add dret instruction and debug CSRs. (#5) | Tim Newsome | 3 | -0/+27 | |
2016-05-13 | Remove arg lists from latex tables | Andrew Waterman | 1 | -42/+1 | |
2016-05-13 | Rename "Device Interrupt" to "External Interrupt" | Andrew Waterman | 1 | -3/+6 | |
2016-05-02 | Remove mipi registers | Andrew Waterman | 1 | -1/+0 | |
IPI pending registers will live outside the core, so they can cause wakeup. | |||||
2016-05-02 | Remove tohost/fromhost | Andrew Waterman | 1 | -2/+0 | |
2016-04-30 | Remove mcfgaddr; change memory map | Andrew Waterman | 2 | -5/+7 | |
2016-04-30 | Remove mtimecmp | Andrew Waterman | 1 | -2/+0 | |
2016-04-30 | ERET -> xRET | Andrew Waterman | 3 | -7/+9 | |
2016-04-06 | Remove nonstandard stats, uarch CSRs | Andrew Waterman | 1 | -21/+0 | |
2016-03-10 | Allow immediates for write_csr; check for signedness | Andrew Waterman | 1 | -6/+12 | |
2016-03-10 | Reflect new location of encoding.h in riscv-pk | Andrew Waterman | 1 | -1/+1 | |
2016-03-03 | Update CSR encoding | Andrew Waterman | 2 | -2/+24 | |
2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -30/+14 | |
2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 2 | -21/+21 | |
2016-02-05 | WIP on priv spec v1.9 | Andrew Waterman | 3 | -44/+44 | |
2016-01-13 | remove hwachaV3 definitions | Colin Schmidt | 4 | -194/+1 | |
2015-11-12 | add miobase, mipi; drop send_ipi | Andrew Waterman | 1 | -1/+2 | |
2015-11-06 | Revert "Revert "Enable the four custom instructions"" | Andrew Waterman | 1 | -1/+1 | |
This reverts commit fe5742618c1732be6000cccfbed3432596dea9e4. | |||||
2015-10-20 | Update to hopefully final RVC 1.9 encoding | Andrew Waterman | 1 | -8/+6 | |
2015-10-12 | rvc 1.8 candidate | Andrew Waterman | 2 | -21/+21 | |
2015-10-05 | move towards RVC 1.8 | Andrew Waterman | 2 | -34/+44 | |
2015-09-28 | In C headers, keep instructions in original input order | Andrew Waterman | 1 | -2/+2 | |
2015-09-28 | Include pseudo-ops in inst.chisel | Andrew Waterman | 1 | -2/+2 | |
2015-09-08 | No need to provide GCC with encoding.h anymore | Andrew Waterman | 1 | -2/+1 | |
2015-09-08 | Use BitPat instead of Bits for Chisel3 | Andrew Waterman | 1 | -1/+1 | |
2015-09-08 | update to latest RVC proposal | Andrew Waterman | 5 | -52/+35 | |
2015-09-02 | Remove automatically-generated files | Andrew Waterman | 3 | -2391/+2 | |
2015-07-28 | Fix DECLARE_CAUSE macros | Andrew Waterman | 1 | -1/+1 | |
2015-07-05 | New machine-mode timer facility | Andrew Waterman | 2 | -3/+3 | |
2015-05-31 | RVC v1.7 encoding | Andrew Waterman | 3 | -22/+65 | |
2015-05-14 | Fix VM, MIP encoding | Andrew Waterman | 1 | -6/+6 | |
2015-05-09 | Update to privileged architecture version 1.7 | Andrew Waterman | 6 | -124/+243 | |
2015-04-02 | Distinguish Sv39/Sv48; reserve some PPN bits | Andrew Waterman | 2 | -5/+7 | |
2015-03-30 | RVC draft | Andrew Waterman | 3 | -51/+24 | |
2015-03-24 | New virtual memory implementation (Sv39) | Andrew Waterman | 1 | -17/+38 | |
2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 3 | -32/+20 | |
2015-03-16 | vxcpthold exposes the first source operand | Yunsup Lee | 1 | -1/+1 | |
2015-03-12 | Add hcall instruction | Andrew Waterman | 2 | -0/+2 | |
2015-03-12 | Add referenced/dirty bits to PTE | Andrew Waterman | 1 | -0/+2 | |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 5 | -124/+206 | |
2014-12-14 | update location of headers for new ABI/toolchain | Colin Schmidt | 1 | -2/+2 | |
2014-11-22 | Revert "Enable the four custom instructions" | Yunsup Lee | 1 | -1/+1 | |
This reverts commit 70b52dd5fa74b5968a20ded22df4ae3a9a76d7f4. Refactoring support for custom instructions. | |||||
2014-10-24 | Merge branch 'pr/1' | Yunsup Lee | 1 | -1/+1 | |
Conflicts: Makefile | |||||
2014-10-23 | Prevent regenerating the Hwacha spike header by default | Albert Ou | 1 | -8/+7 | |
Not every instruction in the main opcodes file is implemented by Hwacha; at present, updating opcodes_hwacha_ut.h requires manual culling of the unneeded instructions to avoid breaking the spike build. | |||||
2014-10-23 | Enable the four custom instructions | Arun Thomas | 1 | -1/+1 | |
Will update encoding.h in the following components: * riscv-isa-sim * riscv-pk * riscv-test-env | |||||
2014-04-03 | Move stats register | Stephen Twigg | 2 | -3/+3 | |
2014-04-03 | Add hwacha spike header file target | Stephen Twigg | 1 | -1/+10 | |