| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2017-11-27 | Don't copy encoding.h to binutils anymore | Andrew Waterman | 1 | -4/+0 | |
| Now that binutils is upstream, we maintain that file manually. | |||||
| 2017-11-27 | Generate encoding.h for OpenOCD as well. (#16) | Tim Newsome | 1 | -2/+3 | |
| 2017-05-17 | Merge remote-tracking branch 'origin/priv-1.10' | Palmer Dabbelt | 5 | -48/+87 | |
| 2017-05-07 | SB->B; UJ->J | Andrew Waterman | 1 | -2/+2 | |
| 2017-05-07 | Add UXl/SXL | Andrew Waterman | 1 | -0/+3 | |
| 2017-04-25 | Add ECALL/EBREAK to privileged instruction table | Andrew Waterman | 1 | -0/+2 | |
| 2017-04-25 | FMV.X.S/FMV.S.X -> FMV.X.W/FMV.W.X | Andrew Waterman | 3 | -4/+8 | |
| 2017-04-25 | Remove hret instruction | Andrew Waterman | 2 | -2/+1 | |
| 2017-03-31 | Add LICENSE | Andrew Waterman | 1 | -0/+24 | |
| 2017-03-31 | Support generating Go code (#3) | Benjamin Barenblat | 3 | -0/+45 | |
| * Support generating Go code Generate Go code for the RISC-V Go port <https://github.com/riscv/riscv-go>. * Clarify use of yank in Go backend * Go: Also generate funct3, csr, and funct7 encodings * Go: Emit all instructions Changes to the RISC-V Go implementation obviate the need for GO_UNUSED_INSTRUCTIONS. * Go: Print CSRs as signed values * Go: Update parse-opcodes to use obj.As See https://github.com/golang/go/commit/0d9258a830c585. * Go: Return errors out of band * Go: Return 'ok' status instead of 'err' status Also clean up imports. * Go: Make gofmt-clean * Go: Return rs2 value for each instructions Some binary floating-point instructions (ab)use the rs2 value to hold additional instruction data, so we need that data in the Go assembler. | |||||
| 2017-03-30 | New PMP encoding | Andrew Waterman | 1 | -5/+6 | |
| 2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 2 | -6/+8 | |
| 2017-03-23 | Add PMP | Andrew Waterman | 2 | -1/+32 | |
| 2017-03-23 | Add TW/TVM/TSR fields to mstatus | Andrew Waterman | 1 | -1/+4 | |
| 2017-03-09 | New counter-enable mechanism | Andrew Waterman | 1 | -2/+2 | |
| 2017-03-09 | Update SPTBR fields | Andrew Waterman | 1 | -14/+9 | |
| 2017-02-20 | Use gcc csr register constraint | Andrew Waterman | 1 | -16/+4 | |
| 2017-02-20 | Remove sfence.vm and add sfence.vma | Andrew Waterman | 2 | -6/+4 | |
| 2017-02-20 | Drop mstatus.VM field | Andrew Waterman | 1 | -1/+0 | |
| 2017-02-14 | Don't update binutils' riscv-opc.h automatically anymore | Andrew Waterman | 1 | -1/+1 | |
| It's upstreamed, so avoid the false impression it can easily change. | |||||
| 2017-02-08 | Encode VM type in sptbr, not mstatus | Andrew Waterman | 1 | -0/+14 | |
| https://github.com/riscv/riscv-isa-manual/issues/4 | |||||
| 2016-12-21 | Add Q extension | Kito Cheng | 1 | -0/+39 | |
| 2016-12-21 | Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space | Kito Cheng | 1 | -1/+1 | |
| 2016-12-06 | avoid non-standard predefined macros | Andrew Waterman | 1 | -1/+1 | |
| 2016-08-26 | Renumber misa; add performance counter CSRs | Andrew Waterman | 1 | -33/+154 | |
| 2016-08-26 | Add mcontrol type constants. (#11) | Tim Newsome | 1 | -0/+3 | |
| 2016-08-25 | Re-rename trigger registers to be 1-based | Andrew Waterman | 1 | -3/+3 | |
| 2016-08-25 | Make hardware triggers match latest spec. | Tim Newsome | 2 | -22/+34 | |
| 2016-07-06 | Update to new PTE format | Andrew Waterman | 1 | -33/+10 | |
| 2016-06-30 | Remove instructions from privilege spec that are already in user spec | Andrew Waterman | 1 | -5/+2 | |
| 2016-06-18 | Add README | Andrew Waterman | 1 | -0/+10 | |
| Closes #6 | |||||
| 2016-06-17 | Remove sasid (it's merged into sptbr now) | Andrew Waterman | 1 | -1/+0 | |
| 2016-06-09 | Update breakpoint spec | Andrew Waterman | 1 | -8/+15 | |
| 2016-06-08 | Add breakpoint CSRs | Andrew Waterman | 2 | -0/+14 | |
| 2016-06-03 | Keep DCSR_XDEBUGVER unsigned. | Tim Newsome | 1 | -1/+1 | |
| 2016-06-01 | Update path to binutils | Andrew Waterman | 1 | -1/+1 | |
| 2016-06-01 | Add dret instruction and debug CSRs. (#5) | Tim Newsome | 3 | -0/+27 | |
| 2016-05-13 | Remove arg lists from latex tables | Andrew Waterman | 1 | -42/+1 | |
| 2016-05-13 | Rename "Device Interrupt" to "External Interrupt" | Andrew Waterman | 1 | -3/+6 | |
| 2016-05-02 | Remove mipi registers | Andrew Waterman | 1 | -1/+0 | |
| IPI pending registers will live outside the core, so they can cause wakeup. | |||||
| 2016-05-02 | Remove tohost/fromhost | Andrew Waterman | 1 | -2/+0 | |
| 2016-04-30 | Remove mcfgaddr; change memory map | Andrew Waterman | 2 | -5/+7 | |
| 2016-04-30 | Remove mtimecmp | Andrew Waterman | 1 | -2/+0 | |
| 2016-04-30 | ERET -> xRET | Andrew Waterman | 3 | -7/+9 | |
| 2016-04-06 | Remove nonstandard stats, uarch CSRs | Andrew Waterman | 1 | -21/+0 | |
| 2016-03-10 | Allow immediates for write_csr; check for signedness | Andrew Waterman | 1 | -6/+12 | |
| 2016-03-10 | Reflect new location of encoding.h in riscv-pk | Andrew Waterman | 1 | -1/+1 | |
| 2016-03-03 | Update CSR encoding | Andrew Waterman | 2 | -2/+24 | |
| 2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 1 | -30/+14 | |
| 2016-02-28 | WIP on priv spec v1.9 | Andrew Waterman | 2 | -21/+21 | |
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index : riscv-tools/riscv-opcodes.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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