Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2015-03-17 | Merge [shm]call into ecall, [shm]ret into eret | Andrew Waterman | 3 | -32/+20 | |
2015-03-16 | vxcpthold exposes the first source operand | Yunsup Lee | 1 | -1/+1 | |
2015-03-12 | Add hcall instruction | Andrew Waterman | 2 | -0/+2 | |
2015-03-12 | Add referenced/dirty bits to PTE | Andrew Waterman | 1 | -0/+2 | |
2015-03-12 | Update to new privileged spec | Andrew Waterman | 5 | -124/+206 | |
2014-12-14 | update location of headers for new ABI/toolchain | Colin Schmidt | 1 | -2/+2 | |
2014-11-22 | Revert "Enable the four custom instructions" | Yunsup Lee | 1 | -1/+1 | |
This reverts commit 70b52dd5fa74b5968a20ded22df4ae3a9a76d7f4. Refactoring support for custom instructions. | |||||
2014-10-24 | Merge branch 'pr/1' | Yunsup Lee | 1 | -1/+1 | |
Conflicts: Makefile | |||||
2014-10-23 | Prevent regenerating the Hwacha spike header by default | Albert Ou | 1 | -8/+7 | |
Not every instruction in the main opcodes file is implemented by Hwacha; at present, updating opcodes_hwacha_ut.h requires manual culling of the unneeded instructions to avoid breaking the spike build. | |||||
2014-10-23 | Enable the four custom instructions | Arun Thomas | 1 | -1/+1 | |
Will update encoding.h in the following components: * riscv-isa-sim * riscv-pk * riscv-test-env | |||||
2014-04-03 | Move stats register | Stephen Twigg | 2 | -3/+3 | |
2014-04-03 | Add hwacha spike header file target | Stephen Twigg | 1 | -1/+10 | |
2014-03-18 | Add rdcycleh etc. for RV32 | Andrew Waterman | 4 | -45/+90 | |
2014-03-11 | Fix syntax error in generated opcodes | Andrew Waterman | 2 | -5/+5 | |
2014-03-11 | New FP encoding | Andrew Waterman | 5 | -309/+367 | |
2014-03-06 | Add fclass.{s|d} instructions | Andrew Waterman | 4 | -42/+68 | |
2014-03-02 | add hwacha vfmsv instructions | Yunsup Lee | 1 | -1/+3 | |
2014-02-14 | Renumber uarch CSRs into custom CSR space | Andrew Waterman | 2 | -32/+32 | |
2014-02-06 | Reserve 16 uarch-specific read-only userspace counters | Andrew Waterman | 3 | -0/+56 | |
2014-02-03 | Add vfmvv, vfmsv instructions, remove vsetprec | Quan Nguyen | 1 | -1/+3 | |
2014-01-21 | Add DECLARE_CAUSE macro | Andrew Waterman | 1 | -0/+5 | |
2014-01-21 | Move microthread-specific opcodes to opcodes-hwacha-ut | Quan Nguyen | 2 | -8/+8 | |
2014-01-21 | Auto-generate exception cause numbers | Andrew Waterman | 3 | -13/+57 | |
2014-01-20 | Merge branch 'confprec' | Quan Nguyen | 3 | -1/+57 | |
Conflicts: Makefile | |||||
2014-01-13 | swap JAL/JALR again | Andrew Waterman | 3 | -9/+9 | |
2013-12-09 | New RDCYCLE encoding | Andrew Waterman | 4 | -100/+99 | |
2013-11-29 | Add vsetprec instructionconfprec | Quan Nguyen | 1 | -0/+1 | |
2013-11-25 | New privileged ISA | Andrew Waterman | 9 | -178/+433 | |
2013-11-24 | Merge branch 'master' into confprec | Quan Nguyen | 5 | -59/+100 | |
Conflicts: Makefile | |||||
2013-11-24 | Add line in Makefile to parse confprec | Quan Nguyen | 1 | -0/+1 | |
2013-11-22 | add missing imm for stores | Yunsup Lee | 2 | -6/+7 | |
2013-11-21 | fix slli/slliw encoding bug | Yunsup Lee | 4 | -7/+8 | |
2013-10-29 | changes to the instr-table | Yunsup Lee | 2 | -45/+85 | |
2013-10-27 | Move half-precision opcodes to opcodes-hwacha-ut | Quan Nguyen | 3 | -41/+57 | |
2013-10-27 | Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprec | Quan Nguyen | 1 | -0/+1 | |
2013-10-18 | add gitignore | Yunsup Lee | 1 | -0/+1 | |
2013-10-17 | Add half-precision floating-point instructions | Quan Nguyen | 2 | -2/+44 | |
* Add opcodes-hwacha-pseudo to be produced as well, or else GCC will complain. | |||||
2013-10-17 | add hwacha exception support | Yunsup Lee | 1 | -0/+3 | |
2013-10-17 | custom-1 opcodes are now 0x0A | Yunsup Lee | 1 | -12/+12 | |
2013-10-10 | revamp hwacha-v3 opcodes | Yunsup Lee | 3 | -116/+115 | |
2013-09-21 | Fix funct field in tables. | Andrew Waterman | 2 | -53/+53 | |
2013-09-21 | Remove old file | Andrew Waterman | 1 | -160/+0 | |
2013-09-21 | Update ISA encoding | Andrew Waterman | 6 | -1271/+1477 | |
2013-08-07 | hwacha v3: inst format follows the new rocket accelerator extensions | Yunsup Lee | 2 | -132/+114 | |
2013-08-06 | Rename MTFSR/MFFSR to FSSR/FRSR | Andrew Waterman | 4 | -8/+8 | |
2013-08-06 | Add custom opcode space | Andrew Waterman | 2 | -1/+29 | |
2013-07-31 | HW ignores upper bits of fence, but SW supplies 0 | Andrew Waterman | 3 | -22/+28 | |
2013-07-31 | Swap J and JALR encodings | Andrew Waterman | 3 | -11/+11 | |
2013-07-26 | change supervisor encoding | Yunsup Lee | 1 | -5/+5 | |
2013-07-26 | tweaks | Yunsup Lee | 2 | -76/+100 | |