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riscv-tools/riscv-opcodes.git
confprec
debug
incoresemi-migration-to-new-format
latex-based-output-refactor
llvm-encodings
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mvp
riscv-bitmanip
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Author
Files
Lines
2017-03-09
New counter-enable mechanism
Andrew Waterman
1
-2
/
+2
2017-03-09
Update SPTBR fields
Andrew Waterman
1
-14
/
+9
2017-02-20
Use gcc csr register constraint
Andrew Waterman
1
-16
/
+4
2017-02-20
Remove sfence.vm and add sfence.vma
Andrew Waterman
2
-6
/
+4
2017-02-20
Drop mstatus.VM field
Andrew Waterman
1
-1
/
+0
2017-02-14
Don't update binutils' riscv-opc.h automatically anymore
Andrew Waterman
1
-1
/
+1
2017-02-08
Encode VM type in sptbr, not mstatus
Andrew Waterman
1
-0
/
+14
2016-12-21
Add Q extension
Kito Cheng
1
-0
/
+39
2016-12-21
Fix first line of riscv-opc.h, gnu coding style need end with 1 dot and 2 space
Kito Cheng
1
-1
/
+1
2016-12-06
avoid non-standard predefined macros
Andrew Waterman
1
-1
/
+1
2016-08-26
Renumber misa; add performance counter CSRs
Andrew Waterman
1
-33
/
+154
2016-08-26
Add mcontrol type constants. (#11)
Tim Newsome
1
-0
/
+3
2016-08-25
Re-rename trigger registers to be 1-based
Andrew Waterman
1
-3
/
+3
2016-08-25
Make hardware triggers match latest spec.
Tim Newsome
2
-22
/
+34
2016-07-06
Update to new PTE format
Andrew Waterman
1
-33
/
+10
2016-06-30
Remove instructions from privilege spec that are already in user spec
Andrew Waterman
1
-5
/
+2
2016-06-18
Add README
Andrew Waterman
1
-0
/
+10
2016-06-17
Remove sasid (it's merged into sptbr now)
Andrew Waterman
1
-1
/
+0
2016-06-09
Update breakpoint spec
Andrew Waterman
1
-8
/
+15
2016-06-08
Add breakpoint CSRs
Andrew Waterman
2
-0
/
+14
2016-06-03
Keep DCSR_XDEBUGVER unsigned.
Tim Newsome
1
-1
/
+1
2016-06-01
Update path to binutils
Andrew Waterman
1
-1
/
+1
2016-06-01
Add dret instruction and debug CSRs. (#5)
Tim Newsome
3
-0
/
+27
2016-05-13
Remove arg lists from latex tables
Andrew Waterman
1
-42
/
+1
2016-05-13
Rename "Device Interrupt" to "External Interrupt"
Andrew Waterman
1
-3
/
+6
2016-05-02
Remove mipi registers
Andrew Waterman
1
-1
/
+0
2016-05-02
Remove tohost/fromhost
Andrew Waterman
1
-2
/
+0
2016-04-30
Remove mcfgaddr; change memory map
Andrew Waterman
2
-5
/
+7
2016-04-30
Remove mtimecmp
Andrew Waterman
1
-2
/
+0
2016-04-30
ERET -> xRET
Andrew Waterman
3
-7
/
+9
2016-04-06
Remove nonstandard stats, uarch CSRs
Andrew Waterman
1
-21
/
+0
2016-03-10
Allow immediates for write_csr; check for signedness
Andrew Waterman
1
-6
/
+12
2016-03-10
Reflect new location of encoding.h in riscv-pk
Andrew Waterman
1
-1
/
+1
2016-03-03
Update CSR encoding
Andrew Waterman
2
-2
/
+24
2016-02-28
WIP on priv spec v1.9
Andrew Waterman
1
-30
/
+14
2016-02-28
WIP on priv spec v1.9
Andrew Waterman
2
-21
/
+21
2016-02-05
WIP on priv spec v1.9
Andrew Waterman
3
-44
/
+44
2016-01-13
remove hwachaV3 definitions
Colin Schmidt
4
-194
/
+1
2015-11-12
add miobase, mipi; drop send_ipi
Andrew Waterman
1
-1
/
+2
2015-11-06
Revert "Revert "Enable the four custom instructions""
Andrew Waterman
1
-1
/
+1
2015-10-20
Update to hopefully final RVC 1.9 encoding
Andrew Waterman
1
-8
/
+6
2015-10-12
rvc 1.8 candidate
Andrew Waterman
2
-21
/
+21
2015-10-05
move towards RVC 1.8
Andrew Waterman
2
-34
/
+44
2015-09-28
In C headers, keep instructions in original input order
Andrew Waterman
1
-2
/
+2
2015-09-28
Include pseudo-ops in inst.chisel
Andrew Waterman
1
-2
/
+2
2015-09-08
No need to provide GCC with encoding.h anymore
Andrew Waterman
1
-2
/
+1
2015-09-08
Use BitPat instead of Bits for Chisel3
Andrew Waterman
1
-1
/
+1
2015-09-08
update to latest RVC proposal
Andrew Waterman
5
-52
/
+35
2015-09-02
Remove automatically-generated files
Andrew Waterman
3
-2391
/
+2
2015-07-28
Fix DECLARE_CAUSE macros
Andrew Waterman
1
-1
/
+1
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