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riscv-tools/riscv-opcodes.git
confprec
debug
incoresemi-migration-to-new-format
latex-based-output-refactor
llvm-encodings
master
mvp
riscv-bitmanip
rnmi
rvv
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Files
Lines
2015-09-28
In C headers, keep instructions in original input order
Andrew Waterman
1
-2
/
+2
2015-09-28
Include pseudo-ops in inst.chisel
Andrew Waterman
1
-2
/
+2
2015-09-08
No need to provide GCC with encoding.h anymore
Andrew Waterman
1
-2
/
+1
2015-09-08
Use BitPat instead of Bits for Chisel3
Andrew Waterman
1
-1
/
+1
2015-09-08
update to latest RVC proposal
Andrew Waterman
5
-52
/
+35
2015-09-02
Remove automatically-generated files
Andrew Waterman
3
-2391
/
+2
2015-07-28
Fix DECLARE_CAUSE macros
Andrew Waterman
1
-1
/
+1
2015-07-05
New machine-mode timer facility
Andrew Waterman
2
-3
/
+3
2015-05-31
RVC v1.7 encoding
Andrew Waterman
3
-22
/
+65
2015-05-14
Fix VM, MIP encoding
Andrew Waterman
1
-6
/
+6
2015-05-09
Update to privileged architecture version 1.7
Andrew Waterman
6
-124
/
+243
2015-04-02
Distinguish Sv39/Sv48; reserve some PPN bits
Andrew Waterman
2
-5
/
+7
2015-03-30
RVC draft
Andrew Waterman
3
-51
/
+24
2015-03-24
New virtual memory implementation (Sv39)
Andrew Waterman
1
-17
/
+38
2015-03-17
Merge [shm]call into ecall, [shm]ret into eret
Andrew Waterman
3
-32
/
+20
2015-03-16
vxcpthold exposes the first source operand
Yunsup Lee
1
-1
/
+1
2015-03-12
Add hcall instruction
Andrew Waterman
2
-0
/
+2
2015-03-12
Add referenced/dirty bits to PTE
Andrew Waterman
1
-0
/
+2
2015-03-12
Update to new privileged spec
Andrew Waterman
5
-124
/
+206
2014-12-14
update location of headers for new ABI/toolchain
Colin Schmidt
1
-2
/
+2
2014-11-22
Revert "Enable the four custom instructions"
Yunsup Lee
1
-1
/
+1
2014-10-24
Merge branch 'pr/1'
Yunsup Lee
1
-1
/
+1
2014-10-23
Prevent regenerating the Hwacha spike header by default
Albert Ou
1
-8
/
+7
2014-10-23
Enable the four custom instructions
Arun Thomas
1
-1
/
+1
2014-04-03
Move stats register
Stephen Twigg
2
-3
/
+3
2014-04-03
Add hwacha spike header file target
Stephen Twigg
1
-1
/
+10
2014-03-18
Add rdcycleh etc. for RV32
Andrew Waterman
4
-45
/
+90
2014-03-11
Fix syntax error in generated opcodes
Andrew Waterman
2
-5
/
+5
2014-03-11
New FP encoding
Andrew Waterman
5
-309
/
+367
2014-03-06
Add fclass.{s|d} instructions
Andrew Waterman
4
-42
/
+68
2014-03-02
add hwacha vfmsv instructions
Yunsup Lee
1
-1
/
+3
2014-02-14
Renumber uarch CSRs into custom CSR space
Andrew Waterman
2
-32
/
+32
2014-02-06
Reserve 16 uarch-specific read-only userspace counters
Andrew Waterman
3
-0
/
+56
2014-02-03
Add vfmvv, vfmsv instructions, remove vsetprec
Quan Nguyen
1
-1
/
+3
2014-01-21
Add DECLARE_CAUSE macro
Andrew Waterman
1
-0
/
+5
2014-01-21
Move microthread-specific opcodes to opcodes-hwacha-ut
Quan Nguyen
2
-8
/
+8
2014-01-21
Auto-generate exception cause numbers
Andrew Waterman
3
-13
/
+57
2014-01-20
Merge branch 'confprec'
Quan Nguyen
3
-1
/
+57
2014-01-13
swap JAL/JALR again
Andrew Waterman
3
-9
/
+9
2013-12-09
New RDCYCLE encoding
Andrew Waterman
4
-100
/
+99
2013-11-29
Add vsetprec instruction
confprec
Quan Nguyen
1
-0
/
+1
2013-11-25
New privileged ISA
Andrew Waterman
9
-178
/
+433
2013-11-24
Merge branch 'master' into confprec
Quan Nguyen
5
-59
/
+100
2013-11-24
Add line in Makefile to parse confprec
Quan Nguyen
1
-0
/
+1
2013-11-22
add missing imm for stores
Yunsup Lee
2
-6
/
+7
2013-11-21
fix slli/slliw encoding bug
Yunsup Lee
4
-7
/
+8
2013-10-29
changes to the instr-table
Yunsup Lee
2
-45
/
+85
2013-10-27
Move half-precision opcodes to opcodes-hwacha-ut
Quan Nguyen
3
-41
/
+57
2013-10-27
Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprec
Quan Nguyen
1
-0
/
+1
2013-10-18
add gitignore
Yunsup Lee
1
-0
/
+1
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