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2014-04-03Add hwacha spike header file targetStephen Twigg1-1/+10
2014-03-18Add rdcycleh etc. for RV32Andrew Waterman4-45/+90
2014-03-11Fix syntax error in generated opcodesAndrew Waterman2-5/+5
2014-03-11New FP encodingAndrew Waterman5-309/+367
2014-03-06Add fclass.{s|d} instructionsAndrew Waterman4-42/+68
2014-03-02add hwacha vfmsv instructionsYunsup Lee1-1/+3
2014-02-14Renumber uarch CSRs into custom CSR spaceAndrew Waterman2-32/+32
2014-02-06Reserve 16 uarch-specific read-only userspace countersAndrew Waterman3-0/+56
2014-02-03Add vfmvv, vfmsv instructions, remove vsetprecQuan Nguyen1-1/+3
2014-01-21Add DECLARE_CAUSE macroAndrew Waterman1-0/+5
2014-01-21Move microthread-specific opcodes to opcodes-hwacha-utQuan Nguyen2-8/+8
2014-01-21Auto-generate exception cause numbersAndrew Waterman3-13/+57
2014-01-20Merge branch 'confprec'Quan Nguyen3-1/+57
2014-01-13swap JAL/JALR againAndrew Waterman3-9/+9
2013-12-09New RDCYCLE encodingAndrew Waterman4-100/+99
2013-11-29Add vsetprec instructionconfprecQuan Nguyen1-0/+1
2013-11-25New privileged ISAAndrew Waterman9-178/+433
2013-11-24Merge branch 'master' into confprecQuan Nguyen5-59/+100
2013-11-24Add line in Makefile to parse confprecQuan Nguyen1-0/+1
2013-11-22add missing imm for storesYunsup Lee2-6/+7
2013-11-21fix slli/slliw encoding bugYunsup Lee4-7/+8
2013-10-29changes to the instr-tableYunsup Lee2-45/+85
2013-10-27Move half-precision opcodes to opcodes-hwacha-utQuan Nguyen3-41/+57
2013-10-27Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprecQuan Nguyen1-0/+1
2013-10-18add gitignoreYunsup Lee1-0/+1
2013-10-17Add half-precision floating-point instructionsQuan Nguyen2-2/+44
2013-10-17add hwacha exception supportYunsup Lee1-0/+3
2013-10-17custom-1 opcodes are now 0x0AYunsup Lee1-12/+12
2013-10-10revamp hwacha-v3 opcodesYunsup Lee3-116/+115
2013-09-21Fix funct field in tables.Andrew Waterman2-53/+53
2013-09-21Remove old fileAndrew Waterman1-160/+0
2013-09-21Update ISA encodingAndrew Waterman6-1271/+1477
2013-08-07hwacha v3: inst format follows the new rocket accelerator extensionsYunsup Lee2-132/+114
2013-08-06Rename MTFSR/MFFSR to FSSR/FRSRAndrew Waterman4-8/+8
2013-08-06Add custom opcode spaceAndrew Waterman2-1/+29
2013-07-31HW ignores upper bits of fence, but SW supplies 0Andrew Waterman3-22/+28
2013-07-31Swap J and JALR encodingsAndrew Waterman3-11/+11
2013-07-26change supervisor encodingYunsup Lee1-5/+5
2013-07-26tweaksYunsup Lee2-76/+100
2013-07-26Factor out Hwacha/RVC and rename MFTX/MXTF to FMVAndrew Waterman7-326/+203
2013-07-25Refactor parse-opcodesAndrew Waterman4-1411/+924
2013-07-25Remove JALR static hintsAndrew Waterman1-3/+1
2013-07-23Remove CFLUSHAndrew Waterman1-1/+0
2013-04-17add auipc, lr, scAndrew Waterman5-13/+58
2012-03-24new supervisor modeAndrew Waterman2-32/+30
2012-03-18change vector fence names/encodingAndrew Waterman4-34/+10
2012-03-18clean up vector exception instructionsYunsup Lee2-14/+19
2012-03-13add more instructions for vector exception handlingYunsup Lee2-2/+9
2012-03-13add vvcfg,vtcfgYunsup Lee2-0/+4
2012-03-13opcodes cleanupYunsup Lee3-14/+12
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