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2020-03-29Using OrderedDict to keep encodings for match/mask. (#38)Kito Cheng1-2/+3
- Prevent got different result in different python env.
2020-03-28Add FP->int truncating conversionsAndrew Waterman1-17/+23
See https://github.com/riscv/riscv-v-spec/pull/403/
2020-03-28Add vfslide1up/downAndrew Waterman1-8/+10
See https://github.com/riscv/riscv-v-spec/pull/402/
2020-03-03Factor out RVC opcodes into per-extension filesAndrew Waterman6-31/+37
2020-03-03Factor out opcodes into per-extension filesAndrew Waterman16-249/+264
2020-03-03Clean up MakefileAndrew Waterman1-9/+12
2020-02-28Add mcountinhibit CSRAndrew Waterman1-0/+1
2020-02-24Add N-extension CSRs and status bits. (#37)michael-roe2-0/+11
2020-02-13Remove mstatus.HPP; move mstatus.VS to its old locationAndrew Waterman1-3/+2
See https://github.com/riscv/riscv-v-spec/pull/351
2019-11-28Remove vamo*q; replace vamo*d with vamo*eAndrew Waterman1-19/+9
2019-11-28Add vmv<nf>r.vAndrew Waterman2-0/+6
2019-11-28Merge branch 'chihminchao-rvv-0.8-draft-20191118'Andrew Waterman3-20/+37
2019-11-28rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wiChih-Min Chao1-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28rvv: add load/store whole registerChih-Min Chao1-2/+7
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28rvv: replace vfncvt suffix with .wChih-Min Chao1-6/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28rvv: add vqmacc variant insnChih-Min Chao1-0/+9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28rvv: add vleb csr register and mstatus.vs fieldChih-Min Chao2-0/+3
1. vleb is read-only CSR to keep vector implementation lenght in byte 2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-15Remove scaled fixed-point multiply-add instructionsAndrew Waterman1-8/+0
See https://github.com/riscv/riscv-v-spec/commit/063b128bd91390c64796fe1e1546a8855fdbaf35
2019-11-15vcompress is encoded with vm=1Andrew Waterman1-1/+1
See https://github.com/riscv/riscv-v-spec/commit/da9ae36997183141521d3f850a935c99535ae73b
2019-11-15Add vaaddu/vasubu; change vaadd/vasub opcodesAndrew Waterman1-5/+10
See https://github.com/riscv/riscv-v-spec/commit/c2f3157e34d3a0f77ccbbc502bdf1530da17aba8
2019-11-11Update encoding of vadc and friendsAndrew Waterman1-10/+10
See https://github.com/riscv/riscv-v-spec/pull/317
2019-11-11Add vfncvt.rod.f.f.v instructionAndrew Waterman1-5/+6
2019-09-17vwmaccsu/us opcodes have been swappedAndrew Waterman1-6/+6
https://github.com/riscv/riscv-v-spec/pull/295
2019-09-12fesvr no longer needs encoding.hAndrew Waterman1-3/+2
2019-09-12Add PAUSE hint instructionAndrew Waterman1-0/+1
2019-08-26More updates to rvv encodingAndrew Waterman1-13/+11
Closes #33
2019-08-03Fix crash introduced by #30Andrew Waterman1-1/+1
2019-08-03(Partially) fix #30 (#31)Tommy Thorn3-42/+47
* (Partially) fix #30 With this change (and a renamed parse-opcodes) it's possible to as a Python module without having to patch the repo. Example: from parse_opcodes import parse_inputs if __name__ == "__main__": (namelist, pseudos, mask, match, arguments) = parse_inputs(["opcodes", "opcodes-rvc"]) * Fix #30: Rename parse-opcode to parse_opcode to enable module use
2019-07-15vext.x.v -> vmv.x.sAndrew Waterman1-1/+1
See https://github.com/riscv/riscv-v-spec/pull/247
2019-07-05Fix encoding of vfclass.v instructionAndrew Waterman1-1/+1
2019-06-28vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcodeAndrew Waterman1-2/+2
See https://github.com/riscv/riscv-v-spec/pull/227
2019-06-19Remove redundant entry from MakefileAndrew Waterman1-1/+1
2019-06-18v-spec 0.7.1-0607 (#29)Chih-Min Chao2-41/+74
* rvv: fault-first also support segement based on 7.8.1, add missing segment supoort for fault first load Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: comparision instructions has 'm' prefix add 'm' prefix since the destination is mask register ref: https://github.com/riscv/riscv-v-spec/pull/181 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: reserved vid.v operand follow v0.7.1 change ref: https://github.com/riscv/riscv-v-spec/issues/160 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add vfrsub.vf follow v-spec 0.7.1 ref: https://github.com/riscv/riscv-v-spec/commit/65d2e233d4f5a95d27edf3fcd8b590b6b3deffbc Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add amo encoding table Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-06-18Add pseudos for RV32 shifts with correct immediate constraintAndrew Waterman2-1/+6
2019-06-16More hypervisor v0.4 updatesAndrew Waterman2-3/+3
2019-06-16Updates for hypervisor v0.4Andrew Waterman1-13/+14
2019-06-11Expand vfunary0 and vfunary1 opcodes into sub-instructionsAndrew Waterman1-2/+20
2019-06-05More V 0.7.1 updatesAndrew Waterman1-12/+10
2019-06-05Some V 0.7.1 updatesAndrew Waterman2-19/+18
2019-06-05VMV.S.X requires vs2=0Andrew Waterman1-2/+2
2019-05-17Merge branch 'chihminchao-rvv-spec-0.7'Andrew Waterman4-4/+414
2019-05-17Expand vmunary0 into its constituent instructionsAndrew Waterman1-1/+6
Note that vmiota is being renamed to viota: https://github.com/riscv/riscv-v-spec/pull/180
2019-05-17vmv/vext/vfmv are reserved when vm=0Andrew Waterman1-4/+4
This is not currently stated in the spec, but there is a pull request to make this explicit: https://github.com/riscv/riscv-v-spec/pull/179
2019-05-17vadc/vsbc require vm=1Andrew Waterman1-5/+5
2019-05-17Add pseudos for masked/unmasked vmerge to help with decodingAndrew Waterman2-2/+12
2019-05-16rvv: vector instruction encodingChih-Min Chao2-2/+380
add most of vector instruction encoding described in v-spec 0.7. except for 'Zvamo' extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-16rvv: add vector register field and control registerChih-Min Chao1-1/+18
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-05-14zimm -> uimm in CSR instruction listingAndrew Waterman1-2/+2
2019-04-26Create RVQ listing in latex tableAndrew Waterman1-0/+16
2019-04-24Add RV128 opcodes (#26)Rustem Yunusov2-4/+10
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