aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-02-23rvv: add vle1/vse1 instructionsChih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-01-23Removing platform-specific definitions (#59)Dan Petrisko1-6/+0
2021-01-22Update Go instruction encoding generation (#34)Joel Sing1-4/+4
Remove the 'ok' value since this is redundant - an invalid instruction can already be identified by a nil return value. Also, include the script flags in the 'DO NOT EDIT' header.
2021-01-17rvb: add xperm.[nbhw] (#56)Chih-Min Chao2-0/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-01-08Add Zfh encodingAndrew Waterman5-1/+46
2021-01-08Update Zba/Zbc/Zbs mnemonics to v0.93; Zbe to v0.94-draftAndrew Waterman2-19/+19
The Zbs v0.93 mnemonics unfortunately collided with Zbe.
2021-01-08Add Zsn to encoding.hAndrew Waterman1-0/+1
2021-01-08Update mstatus/sstatus fields for hypervisor v0.6Andrew Waterman1-2/+8
2020-12-02Merge pull request #55 from chihminchao/rvv-pre-1.0-index-and-quadAndrew Waterman1-31/+36
Rvv pre 1.0 index and quad
2020-12-02rvv: follow change of indexed ordered/unordered load/storeChih-Min Chao1-26/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-12-02rvv: remove quad instructionsChih-Min Chao1-5/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-11-20Remove instructions already removed from RV64BAndrew Waterman1-7/+0
2020-11-13Merge branch 'riscv-bitmanip'Andrew Waterman3-1/+132
2020-11-13Remove subu.wriscv-bitmanipAndrew Waterman1-1/+0
See https://github.com/riscv/riscv-bitmanip/pull/89
2020-11-13Update minu/max encodingsAndrew Waterman1-2/+2
See https://github.com/riscv/riscv-bitmanip/pull/88
2020-11-09Add GitHub Actions file (#53)Pavel I. Kryukov1-0/+21
2020-11-08Support generating Rust code (#52)Ngo Iok Ui (Wu Yu Wei)2-0/+16
2020-10-14Adding four trigger CSRs to the list (#50)Jan Matyas1-0/+4
Adding these four CSRs to parse_opcodes: - 0x7a4 tinfo - 0x7a5 tcontrol - 0x7a8 mcontext - 0x7aa scontext
2020-09-17Add encodings of vfrsqrte7.v and vfrece7.v (#49)Zhen Wei1-0/+2
2020-08-21Add header to .h files. (#48)Tim Newsome1-1/+6
The header explains where the file came from.
2020-08-03Make *.vv operand naming be consistent with type (#46)Zhen Wei1-48/+48
2020-07-31Merge pull request #45 from chihminchao/rvv-and-hypervisorAndrew Waterman8-47/+141
Rvv and hypervisor
2020-07-31hyperviosr: add csr mask and interrupt macro nameChih-Min Chao6-13/+70
This part copy the implementation which has been merged in spike Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-27rvv: add eew 128 ~ 1024 load/store opcodeChih-Min Chao1-33/+65
spike doesn't implement them but the disassembler use it Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-27rvv: add whole ldst pseudo instruction and update reference linkChih-Min Chao2-1/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-21Add vrgatherei16.vvAndrew Waterman1-10/+11
https://github.com/riscv/riscv-v-spec/commit/a67925038b653a75cd7eadb68b9915449941745d
2020-07-21Incorporate whole-register load/store changes in RVV v1.0-draftAndrew Waterman1-2/+20
https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5
2020-06-10Rebase d242e1ed7 onto masterAndrew Waterman3-1/+133
2020-05-12RVV v0.9: AMOs with explicit element widthsAndrew Waterman1-19/+39
https://github.com/riscv/riscv-v-spec/commit/cf03f382ab2e5cfa24874ebc7a190fb0311e3f9a
2020-05-12RVV v0.9: loads/stores with explicit element widthsAndrew Waterman1-45/+33
https://github.com/riscv/riscv-v-spec/commit/aa6032ce9ea4ef8c9f15e7dcb1fa6c7d7ac2d463
2020-05-12RVV v0.9: change vl1r/vs1r opcodesAndrew Waterman1-2/+2
https://github.com/riscv/riscv-v-spec/commit/5a0911c56394cc9ae2b5ade60a019cc82b2f926a
2020-05-12RVV v0.9: new extension instructionsAndrew Waterman1-0/+9
https://github.com/riscv/riscv-v-spec/commit/b6c85cdad7c120780c2b6241b316567740c9affe#diff-34bccafef6cfe01367796362310416df
2020-05-12RVV v0.9: move VFUNARY0/VFUNARY1 opcodesAndrew Waterman1-26/+26
https://github.com/riscv/riscv-v-spec/commit/159124d3da6d1fe693bffc6080ff69876aa66c43#diff-34bccafef6cfe01367796362310416df
2020-05-04Add DCSR_CAUSE_GROUP. (#44)Tim Newsome1-0/+1
2020-04-14rvv: add new vcsr for vector spec 0.9 (#42)Chih-Min Chao1-0/+1
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-07Remove RV128 for now, because it is quite speculativeAndrew Waterman3-13/+2
2020-03-31update csr to draft-20200326-af69f79 (#39)Chih-Min Chao1-1/+16
about two parts 1. hypervisor related 2. missing high part for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-29Using OrderedDict to keep encodings for match/mask. (#38)Kito Cheng1-2/+3
- Prevent got different result in different python env.
2020-03-28Add FP->int truncating conversionsAndrew Waterman1-17/+23
See https://github.com/riscv/riscv-v-spec/pull/403/
2020-03-28Add vfslide1up/downAndrew Waterman1-8/+10
See https://github.com/riscv/riscv-v-spec/pull/402/
2020-03-03Factor out RVC opcodes into per-extension filesAndrew Waterman6-31/+37
2020-03-03Factor out opcodes into per-extension filesAndrew Waterman16-249/+264
2020-03-03Clean up MakefileAndrew Waterman1-9/+12
2020-02-28Add mcountinhibit CSRAndrew Waterman1-0/+1
2020-02-24Add N-extension CSRs and status bits. (#37)michael-roe2-0/+11
2020-02-13Remove mstatus.HPP; move mstatus.VS to its old locationAndrew Waterman1-3/+2
See https://github.com/riscv/riscv-v-spec/pull/351
2019-11-28Remove vamo*q; replace vamo*d with vamo*eAndrew Waterman1-19/+9
2019-11-28Add vmv<nf>r.vAndrew Waterman2-0/+6
2019-11-28Merge branch 'chihminchao-rvv-0.8-draft-20191118'Andrew Waterman3-20/+37
2019-11-28rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wiChih-Min Chao1-12/+12
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
generated by cgit v1.1 at 2024-07-31 19:15:41 +0000