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2021-07-28RVP: v0.5.2 supportChun-Ping Chung3-1/+339
2021-07-28Merge pull request #77 from ben-marshall/masterAndrew Waterman2-66/+4
scalar-crypto: post arch-review aes32* opcode change
2021-07-28scalar-crypto: Remove rv*_only logic.Ben Marshall1-54/+0
- No instructions now share opcodes between RV32 and RV64. - Removing extra logic from parse_opcodes which was added to handle this. - Will also remove downstream logic in Spike to handle this too. On branch master Your branch is ahead of 'origin/master' by 1 commit. (use "git push" to publish your local commits) Changes to be committed: modified: parse_opcodes
2021-07-23scalar-crypto: post arch-review aes32* opcode changeBen Marshall2-12/+4
- After questions from the architecture review and subsequent cryptography task group meetings, we have stopped overlapping the aes32* and aes64* instruction encodings. - We've done this in the name of removing complexity, because opcode space is not as tight as we thought it was when we originally overlapped them. - Change affected by updating the aes32* opcodes only. On branch master Your branch is up-to-date with 'origin/master'. Changes to be committed: modified: opcodes-rv32k modified: parse_opcodes
2021-07-19Virtual memory updates (#76)Daniel Lustig4-1/+16
* Add Svinval instructions * Add PTE defines for Priv 1.12 and Svpbmt
2021-07-18rvv: remove dot and qmac instructions (#75)Chih-Min Chao1-7/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-07-13Updated several RVV instructions (#74)Zhen Wei2-10/+20
2021-06-20Move shift instructions to opcodes-rv64i (#68)Andrew Waterman2-3/+5
The shamt field is 6 bits wide, so doesn't belong in opcodes-rv32i. The opcodes-pseudo file still contains the RV32 versions with shamtw.
2021-06-07Update PTE_N encodingAndrew Waterman1-1/+1
See https://github.com/riscv/riscv-isa-sim/pull/724
2021-06-04scalar-crypto: Opcode updates for v0.9.2 (#66)Ben Marshall4-8/+8
- Change AES32* and SM4* instructions back to regular R-type encoding. On branch scalar-crypto-v0.9.2 Changes to be committed: modified: opcodes-rv32k modified: opcodes-rv64k modified: opcodes-rvk modified: parse_opcodes
2021-04-05Add fence.tso and pause instructionsAndrew Waterman1-2/+2
2021-03-11update vmv.x.s opcode (#65)leahyao1-1/+1
vmv.x.s rd, vs2 dest should be rd
2021-03-08Merge pull request #63 from ben-marshall/scalar-cryptoAndrew Waterman5-3/+136
scalar-crypto: Add opcodes for RV32K, RV64K
2021-02-24Merge pull request #64 from chihminchao/rvv-v0.10Andrew Waterman2-5/+9
Rvv v0.10
2021-02-23rvv: add vsetivliChih-Min Chao2-3/+5
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-23rvv: rename reciprocal instructionsChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-23rvv: add vle1/vse1 instructionsChih-Min Chao1-0/+2
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-02-19scalar-crypto: Apply suggestions from code reviewBen Marshall3-5/+2
Co-authored-by: Megan Wachs <megan@sifive.com>
2021-02-19scalar-crypto: Add opcodes for RV32K, RV64KBen Marshall5-3/+139
- Adds opcodes for RV32 and RV64 scalar crypto. - opcodes-rvk contains encodings which are for RV32 and RV64 base ISAs - opcodes-rv32/64k contains encodings which are for RV32 or RV64 - parse_opcodes has been modified: - Wnable instructions to be listed as either RV32 or RV64 only, allowing these opcodes to overlap. - The C backend has been modifed to emit the "DECLARE_RV32_ONLY" or "DECLARE_RV64_ONLY" macros as needed. - The other backends have not been modified, and may need to be in the future. On branch scalar-crypto Changes to be committed: modified: Makefile new file: opcodes-rv32k new file: opcodes-rv64k new file: opcodes-rvk modified: parse_opcodes
2021-01-23Removing platform-specific definitions (#59)Dan Petrisko1-6/+0
2021-01-22Update Go instruction encoding generation (#34)Joel Sing1-4/+4
Remove the 'ok' value since this is redundant - an invalid instruction can already be identified by a nil return value. Also, include the script flags in the 'DO NOT EDIT' header.
2021-01-17rvb: add xperm.[nbhw] (#56)Chih-Min Chao2-0/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2021-01-08Add Zfh encodingAndrew Waterman5-1/+46
2021-01-08Update Zba/Zbc/Zbs mnemonics to v0.93; Zbe to v0.94-draftAndrew Waterman2-19/+19
The Zbs v0.93 mnemonics unfortunately collided with Zbe.
2021-01-08Add Zsn to encoding.hAndrew Waterman1-0/+1
2021-01-08Update mstatus/sstatus fields for hypervisor v0.6Andrew Waterman1-2/+8
2020-12-02Merge pull request #55 from chihminchao/rvv-pre-1.0-index-and-quadAndrew Waterman1-31/+36
Rvv pre 1.0 index and quad
2020-12-02rvv: follow change of indexed ordered/unordered load/storeChih-Min Chao1-26/+36
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-12-02rvv: remove quad instructionsChih-Min Chao1-5/+0
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-11-20Remove instructions already removed from RV64BAndrew Waterman1-7/+0
2020-11-13Merge branch 'riscv-bitmanip'Andrew Waterman3-1/+132
2020-11-13Remove subu.wriscv-bitmanipAndrew Waterman1-1/+0
See https://github.com/riscv/riscv-bitmanip/pull/89
2020-11-13Update minu/max encodingsAndrew Waterman1-2/+2
See https://github.com/riscv/riscv-bitmanip/pull/88
2020-11-09Add GitHub Actions file (#53)Pavel I. Kryukov1-0/+21
2020-11-08Support generating Rust code (#52)Ngo Iok Ui (Wu Yu Wei)2-0/+16
2020-10-14Adding four trigger CSRs to the list (#50)Jan Matyas1-0/+4
Adding these four CSRs to parse_opcodes: - 0x7a4 tinfo - 0x7a5 tcontrol - 0x7a8 mcontext - 0x7aa scontext
2020-09-17Add encodings of vfrsqrte7.v and vfrece7.v (#49)Zhen Wei1-0/+2
2020-08-21Add header to .h files. (#48)Tim Newsome1-1/+6
The header explains where the file came from.
2020-08-03Make *.vv operand naming be consistent with type (#46)Zhen Wei1-48/+48
2020-07-31Merge pull request #45 from chihminchao/rvv-and-hypervisorAndrew Waterman8-47/+141
Rvv and hypervisor
2020-07-31hyperviosr: add csr mask and interrupt macro nameChih-Min Chao6-13/+70
This part copy the implementation which has been merged in spike Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-27rvv: add eew 128 ~ 1024 load/store opcodeChih-Min Chao1-33/+65
spike doesn't implement them but the disassembler use it Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-27rvv: add whole ldst pseudo instruction and update reference linkChih-Min Chao2-1/+6
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-07-21Add vrgatherei16.vvAndrew Waterman1-10/+11
https://github.com/riscv/riscv-v-spec/commit/a67925038b653a75cd7eadb68b9915449941745d
2020-07-21Incorporate whole-register load/store changes in RVV v1.0-draftAndrew Waterman1-2/+20
https://github.com/riscv/riscv-v-spec/commit/20f673c9aef9ee2ee18a30db52b9a2c5d287deb5
2020-06-10Rebase d242e1ed7 onto masterAndrew Waterman3-1/+133
2020-05-12RVV v0.9: AMOs with explicit element widthsAndrew Waterman1-19/+39
https://github.com/riscv/riscv-v-spec/commit/cf03f382ab2e5cfa24874ebc7a190fb0311e3f9a
2020-05-12RVV v0.9: loads/stores with explicit element widthsAndrew Waterman1-45/+33
https://github.com/riscv/riscv-v-spec/commit/aa6032ce9ea4ef8c9f15e7dcb1fa6c7d7ac2d463
2020-05-12RVV v0.9: change vl1r/vs1r opcodesAndrew Waterman1-2/+2
https://github.com/riscv/riscv-v-spec/commit/5a0911c56394cc9ae2b5ade60a019cc82b2f926a
2020-05-12RVV v0.9: new extension instructionsAndrew Waterman1-0/+9
https://github.com/riscv/riscv-v-spec/commit/b6c85cdad7c120780c2b6241b316567740c9affe#diff-34bccafef6cfe01367796362310416df
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