Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2021-11-02 | Add new hypervisor bits to mstatush | Scott Johnson | 1 | -0/+2 | |
In Spike, I added these by hand in https://github.com/riscv-software-src/riscv-isa-sim/commit/4730be82e63ec8bf4a30aa59afee5e5b58a0fbe4 | |||||
2021-08-25 | Remove vestages of N extension | Andrew Waterman | 2 | -10/+1 | |
N has been deprecated in favor of bare S. | |||||
2021-08-08 | RVP: v0.9.3 support (#79) | marcfedorow | 1 | -1/+0 | |
Removed SWAP16 opcode to avoid overlap with PKBT16 | |||||
2021-08-03 | Fix Svinval rs1 encodings (#78) | Daniel Lustig | 1 | -5/+5 | |
2021-07-28 | Add missing aliases for vle1.v/vse1.v | Andrew Waterman | 1 | -0/+3 | |
2021-07-28 | Merge pull request #60 from riscv/p-ext | Andrew Waterman | 3 | -1/+334 | |
Add RISC-V P Extension v0.9.2 opcodes | |||||
2021-07-28 | RVP: v0.9.2 support | Chun-Ping Chung | 1 | -327/+327 | |
2021-07-28 | RVP: format opcode | Chun-Ping Chung | 1 | -329/+327 | |
2021-07-28 | RVP: v0.9.1 support | Chun-Ping Chung | 2 | -26/+23 | |
2021-07-28 | RVP: v0.5.2 support | Chun-Ping Chung | 3 | -1/+339 | |
2021-07-28 | Merge pull request #77 from ben-marshall/master | Andrew Waterman | 2 | -66/+4 | |
scalar-crypto: post arch-review aes32* opcode change | |||||
2021-07-28 | scalar-crypto: Remove rv*_only logic. | Ben Marshall | 1 | -54/+0 | |
- No instructions now share opcodes between RV32 and RV64. - Removing extra logic from parse_opcodes which was added to handle this. - Will also remove downstream logic in Spike to handle this too. On branch master Your branch is ahead of 'origin/master' by 1 commit. (use "git push" to publish your local commits) Changes to be committed: modified: parse_opcodes | |||||
2021-07-23 | scalar-crypto: post arch-review aes32* opcode change | Ben Marshall | 2 | -12/+4 | |
- After questions from the architecture review and subsequent cryptography task group meetings, we have stopped overlapping the aes32* and aes64* instruction encodings. - We've done this in the name of removing complexity, because opcode space is not as tight as we thought it was when we originally overlapped them. - Change affected by updating the aes32* opcodes only. On branch master Your branch is up-to-date with 'origin/master'. Changes to be committed: modified: opcodes-rv32k modified: parse_opcodes | |||||
2021-07-19 | Virtual memory updates (#76) | Daniel Lustig | 4 | -1/+16 | |
* Add Svinval instructions * Add PTE defines for Priv 1.12 and Svpbmt | |||||
2021-07-18 | rvv: remove dot and qmac instructions (#75) | Chih-Min Chao | 1 | -7/+0 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2021-07-13 | Updated several RVV instructions (#74) | Zhen Wei | 2 | -10/+20 | |
2021-06-20 | Move shift instructions to opcodes-rv64i (#68) | Andrew Waterman | 2 | -3/+5 | |
The shamt field is 6 bits wide, so doesn't belong in opcodes-rv32i. The opcodes-pseudo file still contains the RV32 versions with shamtw. | |||||
2021-06-07 | Update PTE_N encoding | Andrew Waterman | 1 | -1/+1 | |
See https://github.com/riscv/riscv-isa-sim/pull/724 | |||||
2021-06-04 | scalar-crypto: Opcode updates for v0.9.2 (#66) | Ben Marshall | 4 | -8/+8 | |
- Change AES32* and SM4* instructions back to regular R-type encoding. On branch scalar-crypto-v0.9.2 Changes to be committed: modified: opcodes-rv32k modified: opcodes-rv64k modified: opcodes-rvk modified: parse_opcodes | |||||
2021-04-05 | Add fence.tso and pause instructions | Andrew Waterman | 1 | -2/+2 | |
2021-03-11 | update vmv.x.s opcode (#65) | leahyao | 1 | -1/+1 | |
vmv.x.s rd, vs2 dest should be rd | |||||
2021-03-08 | Merge pull request #63 from ben-marshall/scalar-crypto | Andrew Waterman | 5 | -3/+136 | |
scalar-crypto: Add opcodes for RV32K, RV64K | |||||
2021-02-24 | Merge pull request #64 from chihminchao/rvv-v0.10 | Andrew Waterman | 2 | -5/+9 | |
Rvv v0.10 | |||||
2021-02-23 | rvv: add vsetivli | Chih-Min Chao | 2 | -3/+5 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2021-02-23 | rvv: rename reciprocal instructions | Chih-Min Chao | 1 | -2/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2021-02-23 | rvv: add vle1/vse1 instructions | Chih-Min Chao | 1 | -0/+2 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2021-02-19 | scalar-crypto: Apply suggestions from code review | Ben Marshall | 3 | -5/+2 | |
Co-authored-by: Megan Wachs <megan@sifive.com> | |||||
2021-02-19 | scalar-crypto: Add opcodes for RV32K, RV64K | Ben Marshall | 5 | -3/+139 | |
- Adds opcodes for RV32 and RV64 scalar crypto. - opcodes-rvk contains encodings which are for RV32 and RV64 base ISAs - opcodes-rv32/64k contains encodings which are for RV32 or RV64 - parse_opcodes has been modified: - Wnable instructions to be listed as either RV32 or RV64 only, allowing these opcodes to overlap. - The C backend has been modifed to emit the "DECLARE_RV32_ONLY" or "DECLARE_RV64_ONLY" macros as needed. - The other backends have not been modified, and may need to be in the future. On branch scalar-crypto Changes to be committed: modified: Makefile new file: opcodes-rv32k new file: opcodes-rv64k new file: opcodes-rvk modified: parse_opcodes | |||||
2021-01-23 | Removing platform-specific definitions (#59) | Dan Petrisko | 1 | -6/+0 | |
2021-01-22 | Update Go instruction encoding generation (#34) | Joel Sing | 1 | -4/+4 | |
Remove the 'ok' value since this is redundant - an invalid instruction can already be identified by a nil return value. Also, include the script flags in the 'DO NOT EDIT' header. | |||||
2021-01-17 | rvb: add xperm.[nbhw] (#56) | Chih-Min Chao | 2 | -0/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2021-01-08 | Add Zfh encoding | Andrew Waterman | 5 | -1/+46 | |
2021-01-08 | Update Zba/Zbc/Zbs mnemonics to v0.93; Zbe to v0.94-draft | Andrew Waterman | 2 | -19/+19 | |
The Zbs v0.93 mnemonics unfortunately collided with Zbe. | |||||
2021-01-08 | Add Zsn to encoding.h | Andrew Waterman | 1 | -0/+1 | |
2021-01-08 | Update mstatus/sstatus fields for hypervisor v0.6 | Andrew Waterman | 1 | -2/+8 | |
2020-12-02 | Merge pull request #55 from chihminchao/rvv-pre-1.0-index-and-quad | Andrew Waterman | 1 | -31/+36 | |
Rvv pre 1.0 index and quad | |||||
2020-12-02 | rvv: follow change of indexed ordered/unordered load/store | Chih-Min Chao | 1 | -26/+36 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-12-02 | rvv: remove quad instructions | Chih-Min Chao | 1 | -5/+0 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-11-20 | Remove instructions already removed from RV64B | Andrew Waterman | 1 | -7/+0 | |
2020-11-13 | Merge branch 'riscv-bitmanip' | Andrew Waterman | 3 | -1/+132 | |
2020-11-13 | Remove subu.wriscv-bitmanip | Andrew Waterman | 1 | -1/+0 | |
See https://github.com/riscv/riscv-bitmanip/pull/89 | |||||
2020-11-13 | Update minu/max encodings | Andrew Waterman | 1 | -2/+2 | |
See https://github.com/riscv/riscv-bitmanip/pull/88 | |||||
2020-11-09 | Add GitHub Actions file (#53) | Pavel I. Kryukov | 1 | -0/+21 | |
2020-11-08 | Support generating Rust code (#52) | Ngo Iok Ui (Wu Yu Wei) | 2 | -0/+16 | |
2020-10-14 | Adding four trigger CSRs to the list (#50) | Jan Matyas | 1 | -0/+4 | |
Adding these four CSRs to parse_opcodes: - 0x7a4 tinfo - 0x7a5 tcontrol - 0x7a8 mcontext - 0x7aa scontext | |||||
2020-09-17 | Add encodings of vfrsqrte7.v and vfrece7.v (#49) | Zhen Wei | 1 | -0/+2 | |
2020-08-21 | Add header to .h files. (#48) | Tim Newsome | 1 | -1/+6 | |
The header explains where the file came from. | |||||
2020-08-03 | Make *.vv operand naming be consistent with type (#46) | Zhen Wei | 1 | -48/+48 | |
2020-07-31 | Merge pull request #45 from chihminchao/rvv-and-hypervisor | Andrew Waterman | 8 | -47/+141 | |
Rvv and hypervisor | |||||
2020-07-31 | hyperviosr: add csr mask and interrupt macro name | Chih-Min Chao | 6 | -13/+70 | |
This part copy the implementation which has been merged in spike Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> |