Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2020-06-10 | Rebase d242e1ed7 onto master | Andrew Waterman | 3 | -1/+133 | |
2020-05-12 | RVV v0.9: AMOs with explicit element widths | Andrew Waterman | 1 | -19/+39 | |
https://github.com/riscv/riscv-v-spec/commit/cf03f382ab2e5cfa24874ebc7a190fb0311e3f9a | |||||
2020-05-12 | RVV v0.9: loads/stores with explicit element widths | Andrew Waterman | 1 | -45/+33 | |
https://github.com/riscv/riscv-v-spec/commit/aa6032ce9ea4ef8c9f15e7dcb1fa6c7d7ac2d463 | |||||
2020-05-12 | RVV v0.9: change vl1r/vs1r opcodes | Andrew Waterman | 1 | -2/+2 | |
https://github.com/riscv/riscv-v-spec/commit/5a0911c56394cc9ae2b5ade60a019cc82b2f926a | |||||
2020-05-12 | RVV v0.9: new extension instructions | Andrew Waterman | 1 | -0/+9 | |
https://github.com/riscv/riscv-v-spec/commit/b6c85cdad7c120780c2b6241b316567740c9affe#diff-34bccafef6cfe01367796362310416df | |||||
2020-05-12 | RVV v0.9: move VFUNARY0/VFUNARY1 opcodes | Andrew Waterman | 1 | -26/+26 | |
https://github.com/riscv/riscv-v-spec/commit/159124d3da6d1fe693bffc6080ff69876aa66c43#diff-34bccafef6cfe01367796362310416df | |||||
2020-05-04 | Add DCSR_CAUSE_GROUP. (#44) | Tim Newsome | 1 | -0/+1 | |
2020-04-14 | rvv: add new vcsr for vector spec 0.9 (#42) | Chih-Min Chao | 1 | -0/+1 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-04-07 | Remove RV128 for now, because it is quite speculative | Andrew Waterman | 3 | -13/+2 | |
2020-03-31 | update csr to draft-20200326-af69f79 (#39) | Chih-Min Chao | 1 | -1/+16 | |
about two parts 1. hypervisor related 2. missing high part for rv32 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2020-03-29 | Using OrderedDict to keep encodings for match/mask. (#38) | Kito Cheng | 1 | -2/+3 | |
- Prevent got different result in different python env. | |||||
2020-03-28 | Add FP->int truncating conversions | Andrew Waterman | 1 | -17/+23 | |
See https://github.com/riscv/riscv-v-spec/pull/403/ | |||||
2020-03-28 | Add vfslide1up/down | Andrew Waterman | 1 | -8/+10 | |
See https://github.com/riscv/riscv-v-spec/pull/402/ | |||||
2020-03-03 | Factor out RVC opcodes into per-extension files | Andrew Waterman | 6 | -31/+37 | |
2020-03-03 | Factor out opcodes into per-extension files | Andrew Waterman | 16 | -249/+264 | |
2020-03-03 | Clean up Makefile | Andrew Waterman | 1 | -9/+12 | |
2020-02-28 | Add mcountinhibit CSR | Andrew Waterman | 1 | -0/+1 | |
2020-02-24 | Add N-extension CSRs and status bits. (#37) | michael-roe | 2 | -0/+11 | |
2020-02-13 | Remove mstatus.HPP; move mstatus.VS to its old location | Andrew Waterman | 1 | -3/+2 | |
See https://github.com/riscv/riscv-v-spec/pull/351 | |||||
2019-11-28 | Remove vamo*q; replace vamo*d with vamo*e | Andrew Waterman | 1 | -19/+9 | |
2019-11-28 | Add vmv<nf>r.v | Andrew Waterman | 2 | -0/+6 | |
2019-11-28 | Merge branch 'chihminchao-rvv-0.8-draft-20191118' | Andrew Waterman | 3 | -20/+37 | |
2019-11-28 | rvv: replace vnsrl/vnsra/vnclip suffix with .wv/.wv/.wi | Chih-Min Chao | 1 | -12/+12 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-28 | rvv: add load/store whole register | Chih-Min Chao | 1 | -2/+7 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-28 | rvv: replace vfncvt suffix with .w | Chih-Min Chao | 1 | -6/+6 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-28 | rvv: add vqmacc variant insn | Chih-Min Chao | 1 | -0/+9 | |
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-28 | rvv: add vleb csr register and mstatus.vs field | Chih-Min Chao | 2 | -0/+3 | |
1. vleb is read-only CSR to keep vector implementation lenght in byte 2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-11-15 | Remove scaled fixed-point multiply-add instructions | Andrew Waterman | 1 | -8/+0 | |
See https://github.com/riscv/riscv-v-spec/commit/063b128bd91390c64796fe1e1546a8855fdbaf35 | |||||
2019-11-15 | vcompress is encoded with vm=1 | Andrew Waterman | 1 | -1/+1 | |
See https://github.com/riscv/riscv-v-spec/commit/da9ae36997183141521d3f850a935c99535ae73b | |||||
2019-11-15 | Add vaaddu/vasubu; change vaadd/vasub opcodes | Andrew Waterman | 1 | -5/+10 | |
See https://github.com/riscv/riscv-v-spec/commit/c2f3157e34d3a0f77ccbbc502bdf1530da17aba8 | |||||
2019-11-11 | Update encoding of vadc and friends | Andrew Waterman | 1 | -10/+10 | |
See https://github.com/riscv/riscv-v-spec/pull/317 | |||||
2019-11-11 | Add vfncvt.rod.f.f.v instruction | Andrew Waterman | 1 | -5/+6 | |
2019-09-17 | vwmaccsu/us opcodes have been swapped | Andrew Waterman | 1 | -6/+6 | |
https://github.com/riscv/riscv-v-spec/pull/295 | |||||
2019-09-12 | fesvr no longer needs encoding.h | Andrew Waterman | 1 | -3/+2 | |
2019-09-12 | Add PAUSE hint instruction | Andrew Waterman | 1 | -0/+1 | |
2019-08-26 | More updates to rvv encoding | Andrew Waterman | 1 | -13/+11 | |
Closes #33 | |||||
2019-08-03 | Fix crash introduced by #30 | Andrew Waterman | 1 | -1/+1 | |
2019-08-03 | (Partially) fix #30 (#31) | Tommy Thorn | 3 | -42/+47 | |
* (Partially) fix #30 With this change (and a renamed parse-opcodes) it's possible to as a Python module without having to patch the repo. Example: from parse_opcodes import parse_inputs if __name__ == "__main__": (namelist, pseudos, mask, match, arguments) = parse_inputs(["opcodes", "opcodes-rvc"]) * Fix #30: Rename parse-opcode to parse_opcode to enable module use | |||||
2019-07-15 | vext.x.v -> vmv.x.s | Andrew Waterman | 1 | -1/+1 | |
See https://github.com/riscv/riscv-v-spec/pull/247 | |||||
2019-07-05 | Fix encoding of vfclass.v instruction | Andrew Waterman | 1 | -1/+1 | |
2019-06-28 | vmpopc/vmfirst -> vpopc/vfirst; move to VMUNARY0 opcode | Andrew Waterman | 1 | -2/+2 | |
See https://github.com/riscv/riscv-v-spec/pull/227 | |||||
2019-06-19 | Remove redundant entry from Makefile | Andrew Waterman | 1 | -1/+1 | |
2019-06-18 | v-spec 0.7.1-0607 (#29) | Chih-Min Chao | 2 | -41/+74 | |
* rvv: fault-first also support segement based on 7.8.1, add missing segment supoort for fault first load Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: comparision instructions has 'm' prefix add 'm' prefix since the destination is mask register ref: https://github.com/riscv/riscv-v-spec/pull/181 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: reserved vid.v operand follow v0.7.1 change ref: https://github.com/riscv/riscv-v-spec/issues/160 Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add vfrsub.vf follow v-spec 0.7.1 ref: https://github.com/riscv/riscv-v-spec/commit/65d2e233d4f5a95d27edf3fcd8b590b6b3deffbc Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> * rvv: add amo encoding table Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2019-06-18 | Add pseudos for RV32 shifts with correct immediate constraint | Andrew Waterman | 2 | -1/+6 | |
2019-06-16 | More hypervisor v0.4 updates | Andrew Waterman | 2 | -3/+3 | |
2019-06-16 | Updates for hypervisor v0.4 | Andrew Waterman | 1 | -13/+14 | |
2019-06-11 | Expand vfunary0 and vfunary1 opcodes into sub-instructions | Andrew Waterman | 1 | -2/+20 | |
2019-06-05 | More V 0.7.1 updates | Andrew Waterman | 1 | -12/+10 | |
2019-06-05 | Some V 0.7.1 updates | Andrew Waterman | 2 | -19/+18 | |
2019-06-05 | VMV.S.X requires vs2=0 | Andrew Waterman | 1 | -2/+2 | |