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riscv-tools/riscv-opcodes.git
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2013-11-29
Add vsetprec instruction
confprec
Quan Nguyen
1
-0
/
+1
2013-11-24
Merge branch 'master' into confprec
Quan Nguyen
5
-59
/
+100
Conflicts: Makefile
2013-11-24
Add line in Makefile to parse confprec
Quan Nguyen
1
-0
/
+1
2013-11-22
add missing imm for stores
Yunsup Lee
2
-6
/
+7
2013-11-21
fix slli/slliw encoding bug
Yunsup Lee
4
-7
/
+8
2013-10-29
changes to the instr-table
Yunsup Lee
2
-45
/
+85
2013-10-27
Move half-precision opcodes to opcodes-hwacha-ut
Quan Nguyen
3
-41
/
+57
2013-10-27
Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprec
Quan Nguyen
1
-0
/
+1
2013-10-18
add gitignore
Yunsup Lee
1
-0
/
+1
2013-10-17
Add half-precision floating-point instructions
Quan Nguyen
2
-2
/
+44
* Add opcodes-hwacha-pseudo to be produced as well, or else GCC will complain.
2013-10-17
add hwacha exception support
Yunsup Lee
1
-0
/
+3
2013-10-17
custom-1 opcodes are now 0x0A
Yunsup Lee
1
-12
/
+12
2013-10-10
revamp hwacha-v3 opcodes
Yunsup Lee
3
-116
/
+115
2013-09-21
Fix funct field in tables.
Andrew Waterman
2
-53
/
+53
2013-09-21
Remove old file
Andrew Waterman
1
-160
/
+0
2013-09-21
Update ISA encoding
Andrew Waterman
6
-1271
/
+1477
2013-08-07
hwacha v3: inst format follows the new rocket accelerator extensions
Yunsup Lee
2
-132
/
+114
2013-08-06
Rename MTFSR/MFFSR to FSSR/FRSR
Andrew Waterman
4
-8
/
+8
2013-08-06
Add custom opcode space
Andrew Waterman
2
-1
/
+29
2013-07-31
HW ignores upper bits of fence, but SW supplies 0
Andrew Waterman
3
-22
/
+28
2013-07-31
Swap J and JALR encodings
Andrew Waterman
3
-11
/
+11
2013-07-26
change supervisor encoding
Yunsup Lee
1
-5
/
+5
2013-07-26
tweaks
Yunsup Lee
2
-76
/
+100
2013-07-26
Factor out Hwacha/RVC and rename MFTX/MXTF to FMV
Andrew Waterman
7
-326
/
+203
2013-07-25
Refactor parse-opcodes
Andrew Waterman
4
-1411
/
+924
2013-07-25
Remove JALR static hints
Andrew Waterman
1
-3
/
+1
2013-07-23
Remove CFLUSH
Andrew Waterman
1
-1
/
+0
2013-04-17
add auipc, lr, sc
Andrew Waterman
5
-13
/
+58
2012-03-24
new supervisor mode
Andrew Waterman
2
-32
/
+30
2012-03-18
change vector fence names/encoding
Andrew Waterman
4
-34
/
+10
2012-03-18
clean up vector exception instructions
Yunsup Lee
2
-14
/
+19
2012-03-13
add more instructions for vector exception handling
Yunsup Lee
2
-2
/
+9
2012-03-13
add vvcfg,vtcfg
Yunsup Lee
2
-0
/
+4
2012-03-13
opcodes cleanup
Yunsup Lee
3
-14
/
+12
2012-03-10
slight change to vector supervisor instructions
Yunsup Lee
2
-8
/
+8
2012-03-03
new instructions to handle vector exceptions
Yunsup Lee
3
-2
/
+14
2011-06-19
temporary undoing of renaming
Andrew Waterman
5
-0
/
+3585
2011-06-19
Renamed packages
Andrew Waterman
5
-3585
/
+0
2011-06-19
[riscv-isa-run] code cleanup; added README
Andrew Waterman
4
-9
/
+27
2011-06-10
[sim, opcodes] made sim more decoupled from opcodes
Andrew Waterman
2
-60
/
+6
2011-05-29
[sim,opcodes] improved sim build and run performance
Andrew Waterman
2
-47
/
+60
2011-05-18
[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)
Yunsup Lee
1
-2
/
+2
2011-05-15
[opcodes,pk,sim,xcc] resolve a conflict
Yunsup Lee
3
-16
/
+16
2011-05-15
[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
Yunsup Lee
4
-163
/
+251
2011-05-13
tweaked encoding of rdcycle & cousins
Andrew Waterman
3
-14
/
+50
2011-05-06
[opcodes] reordered RVC instructions
Andrew Waterman
2
-20
/
+21
2011-04-24
[xcc,sim,opcodes] added c.addiw
Andrew Waterman
3
-26
/
+4
2011-04-24
[xcc,sim,opcodes] added more RVC instructions
Andrew Waterman
3
-5
/
+47
2011-04-18
[xcc,sim,opcodes] added rvc conditional branches
Andrew Waterman
2
-12
/
+16
2011-04-12
[xcc,pk,sim] added privileged cflush instruction
Andrew Waterman
2
-0
/
+2
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