1 files changed, 70 insertions, 2 deletions
diff --git a/parse_opcodes b/parse_opcodes
index 6f4ccec..6dae82a 100755
--- a/parse_opcodes
+++ b/parse_opcodes
@@ -16,6 +16,7 @@ arguments = {}
 
 arglut = {}
 arglut['rd'] = (11,7)
+arglut['rt'] = (19,15) # source+dest register address. Overlaps rs1.
 arglut['rs1'] = (19,15)
 arglut['rs2'] = (24,20)
 arglut['rs3'] = (31,27)
@@ -35,6 +36,8 @@ arglut['bimm12lo'] = (11,7)
 arglut['zimm'] = (19,15)
 arglut['shamt'] = (25,20)
 arglut['shamtw'] = (24,20)
+arglut['bs'] = (31,30) # byte select for RV32K AES
+arglut['rcon'] = (23,20) # round constant for RV64 AES
 
 # for vectors
 arglut['vd'] = (11,7)
@@ -49,7 +52,54 @@ arglut['simm5'] = (19,15)
 arglut['zimm10'] = (29,20)
 arglut['zimm11'] = (30,20)
 
+#
+# These lists allow instructions which only appear in either the RV32 or
+# RV64 base architectures to overlap their opcodes.
+
+# Instructions which are _only_ in RV32
+rv32_only = [
+    "aes32esmi",
+    "aes32esi",
+    "aes32dsmi",
+    "aes32dsi",
+    "sha512sum0r",
+    "sha512sum1r",
+    "sha512sig0l",
+    "sha512sig0h",
+    "sha512sig1l",
+    "sha512sig1h"
+]
+
+# Instructions which are _only_ in RV64
+rv64_only = [
+    "aes64ks1i",
+    "aes64im",
+    "aes64ks2",
+    "aes64esm",
+    "aes64es",
+    "aes64dsm",
+    "aes64ds",
+    "sha512sum0",
+    "sha512sum1",
+    "sha512sig0",
+    "sha512sig1"
+]
 
+# Check rv32_only and rv64_only don't have shared elements.
+for a in rv32_only:
+    assert (not a in rv64_only), ("Instruction '%s' marked as both RV32 only, and RV64 only." % a)
+
+def different_base_isa(name1, name2):
+    """
+    Check if the two supplied instructions are mutually exclusive on
+    the base ISA they depend on. That is, they can never both be decoded
+    under the same XLEN.
+    """
+    return (name1 in rv32_only) and (name2 in rv64_only) or \
+           (name2 in rv32_only) and (name1 in rv64_only)
+
+#
+# Trap cause codes
 causes = [
   (0x00, 'misaligned fetch'),
   (0x01, 'fetch access'),
@@ -296,6 +346,8 @@ csrs = [
   (0xF12, 'marchid'),
   (0xF13, 'mimpid'),
   (0xF14, 'mhartid'),
+  (0xF15, 'mentropy'), # crypto ext
+  (0x7A9, 'mnoise'),
 ]
 
 csrs32 = [
@@ -398,7 +450,18 @@ def make_c(match,mask):
   for name in namelist:
     name2 = name.replace('.','_')
     print('DECLARE_INSN(%s, MATCH_%s, MASK_%s)' % (name2, name2.upper(), name2.upper()))
-  print('#endif')
+  print("#ifdef DECLARE_RV32_ONLY")
+  for name in namelist:
+    if name in rv32_only:
+      print("DECLARE_RV32_ONLY(%s)" % name)
+  print("#endif") #ifdef DECLARE_RV32_ONLY
+
+  print("#ifdef DECLARE_RV64_ONLY")
+  for name in namelist:
+    if name in rv64_only:
+      print("DECLARE_RV64_ONLY(%s)" % name)
+  print("#endif") # #ifdef DECLARE_RV64_ONLY
+  print('#endif') # #ifdef DECLARE_INSN
 
   print('#ifdef DECLARE_CSR')
   for num, name in csrs+csrs32:
@@ -1101,7 +1164,12 @@ def parse_inputs(args):
       else:
         for name2,match2 in match.items():
           if name2 not in pseudos and (match2 & mymask) == mymatch:
-            sys.exit("%s and %s overlap" % (name,name2))
+            if(different_base_isa(name, name2)):
+              # The instructions cannot collide, as they exist under
+              # different base ISAs.
+              continue
+            else:
+              sys.exit("%s and %s overlap" % (name,name2))
 
       mask[name] = mymask
       match[name] = mymatch