diff options
| -rwxr-xr-x | parse.py | 15 | ||||
| -rw-r--r-- | rv64_zba | 2 | ||||
| -rw-r--r-- | rv64_zbb | 2 | ||||
| -rw-r--r-- | rv64_zbs | 8 | ||||
| -rw-r--r-- | test.py | 3 | ||||
| -rw-r--r-- | unratified/rv64_zbp | 4 | ||||
| -rw-r--r-- | unratified/rv64_zbt | 2 | ||||
| -rw-r--r-- | unratified/rv_b | 4 |
8 files changed, 24 insertions, 16 deletions
@@ -95,6 +95,11 @@ def process_enc_line(line, ext): for (lsb, value, drop) in single_fixed.findall(remaining): lsb = int(lsb, 0) value = int(value, 0) + if encoding[31 - lsb] != '-': + logging.error( + f'{line.split(" ")[0]:<10} has {lsb} bit overlapping in it\'s opcodes' + ) + raise SystemExit(1) encoding[31 - lsb] = str(value) # convert the list of encodings into a single string for match and mask @@ -104,19 +109,19 @@ def process_enc_line(line, ext): # check if all args of the instruction are present in arg_lut present in # constants.py args = single_fixed.sub(' ', remaining).split() - encoding_args = ['-'] * 32 + encoding_args = encoding for a in args: if a not in arg_lut: logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') raise SystemExit(1) else: (msb, lsb) = arg_lut[a] - for ind in range(lsb, msb): + for ind in range(lsb, msb + 1): # overlapping bits - if encoding_args[ind] != '-': - logging.error(f' Found variable {a} in instruction {name} overlapping {encoding_args[ind]} variable') + if encoding_args[31 - ind] != '-': + logging.error(f' Found variable {a} in instruction {name} overlapping {encoding_args[31 - ind]} variable in bit {ind}') raise SystemExit(1) - encoding_args[ind] = a + encoding_args[31 - ind] = a # update the fields of the instruction as a dict and return back along with # the name of the instruction @@ -2,4 +2,4 @@ add.uw rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 sh1add.uw rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3 sh2add.uw rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3 sh3add.uw rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3 -slli.uw rd rs1 31..26=2 shamt 14..12=1 6..2=0x06 1..0=3 +slli.uw rd rs1 31..26=2 shamtd 14..12=1 6..2=0x06 1..0=3 @@ -4,6 +4,6 @@ cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0 rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0=3 rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3 roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3 -rori rd rs1 31..26=0x18 shamt 14..12=5 6..2=0x04 1..0=3 +rori rd rs1 31..26=0x18 shamtd 14..12=5 6..2=0x04 1..0=3 $pseudo_op rv64_zbe::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 $pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 @@ -1,5 +1,5 @@ -bclri rd rs1 31..26=0x12 shamt 14..12=1 6..2=0x04 1..0=3 -bexti rd rs1 31..26=0x12 shamt 14..12=5 6..2=0x04 1..0=3 -binvi rd rs1 31..26=0x1a shamt 14..12=1 6..2=0x04 1..0=3 -bseti rd rs1 31..26=0x0a shamt 14..12=1 6..2=0x04 1..0=3 +bclri rd rs1 31..26=0x12 shamtd 14..12=1 6..2=0x04 1..0=3 +bexti rd rs1 31..26=0x12 shamtd 14..12=5 6..2=0x04 1..0=3 +binvi rd rs1 31..26=0x1a shamtd 14..12=1 6..2=0x04 1..0=3 +bseti rd rs1 31..26=0x0a shamtd 14..12=1 6..2=0x04 1..0=3 @@ -21,6 +21,9 @@ class EncodingLineTest(unittest.TestCase): def test_overlapping(self): self.assertError('jol rd jimm20 6..2=0x00 3..0=7') + self.assertError('jol rd jimm20 6..2=0x00 3=1') + self.assertError('jol rd jimm20 6..2=0x00 10=1') + self.assertError('jol rd jimm20 6..2=0x00 31..10=1') def test_invalid_order(self): self.assertError('jol 2..6=0x1b') diff --git a/unratified/rv64_zbp b/unratified/rv64_zbp index f8c06bd..6ffc33f 100644 --- a/unratified/rv64_zbp +++ b/unratified/rv64_zbp @@ -1,5 +1,5 @@ -grevi rd rs1 31..26=26 shamt 14..12=5 6..2=0x04 1..0=3 -gorci rd rs1 31..26=10 shamt 14..12=5 6..2=0x04 1..0=3 +grevi rd rs1 31..26=26 shamtd 14..12=5 6..2=0x04 1..0=3 +gorci rd rs1 31..26=10 shamtd 14..12=5 6..2=0x04 1..0=3 shfli rd rs1 31..26=2 25=0 shamtw 14..12=1 6..2=0x04 1..0=3 unshfli rd rs1 31..26=2 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 $import rv64_zbe::packw diff --git a/unratified/rv64_zbt b/unratified/rv64_zbt index fcb84b5..d009b73 100644 --- a/unratified/rv64_zbt +++ b/unratified/rv64_zbt @@ -1,6 +1,6 @@ fslw rd rs1 rs2 rs3 26..25=2 14..12=1 6..2=0x0E 1..0=3 fsrw rd rs1 rs2 rs3 26..25=2 14..12=5 6..2=0x0E 1..0=3 fsriw rd rs1 rs3 26..25=2 shamtw 14..12=5 6..2=0x06 1..0=3 -fsri rd rs1 rs3 26=1 shamt 14..12=5 6..2=0x04 1..0=3 +fsri rd rs1 rs3 26=1 shamtd 14..12=5 6..2=0x04 1..0=3 diff --git a/unratified/rv_b b/unratified/rv_b index 4fe7ef0..b0b68b0 100644 --- a/unratified/rv_b +++ b/unratified/rv_b @@ -3,8 +3,8 @@ slo rd rs1 rs2 31..25=16 14..12=1 6..2=0x0C 1..0=3 sro rd rs1 rs2 31..25=16 14..12=5 6..2=0x0C 1..0=3 -sloi rd rs1 31..26=8 shamt 14..12=1 6..2=0x04 1..0=3 -sroi rd rs1 31..26=8 shamt 14..12=5 6..2=0x04 1..0=3 +sloi rd rs1 31..26=8 shamtd 14..12=1 6..2=0x04 1..0=3 +sroi rd rs1 31..26=8 shamtd 14..12=5 6..2=0x04 1..0=3 |