diff options
| -rw-r--r-- | arg_lut.csv | 6 | ||||
| -rw-r--r-- | constants.py | 7 | ||||
| -rw-r--r-- | csrs.csv | 2 | ||||
| -rw-r--r-- | extensions/rv_i | 2 | ||||
| -rw-r--r-- | extensions/rv_zvkn | 15 | ||||
| -rw-r--r-- | extensions/rv_zvks | 15 | ||||
| -rwxr-xr-x | parse.py | 5 | ||||
| -rw-r--r-- | shared_utils.py | 2 | ||||
| -rw-r--r-- | unratified/rv32_zclsd | 9 | ||||
| -rw-r--r-- | unratified/rv32_zilsd | 4 |
10 files changed, 33 insertions, 34 deletions
diff --git a/arg_lut.csv b/arg_lut.csv index ed30b11..820f639 100644 --- a/arg_lut.csv +++ b/arg_lut.csv @@ -97,3 +97,9 @@ "c_rs2", 6, 2 "c_sreg1", 9, 7 "c_sreg2", 4, 2 +"rd_p_e", 4, 3 +"rs2_p_e", 4, 3 +"rd_n0_e", 11, 8 +"c_rs2_e", 6, 3 +"rd_e", 11, 8 +"rs2_e", 24, 21 diff --git a/constants.py b/constants.py index fa59aa7..7959a4b 100644 --- a/constants.py +++ b/constants.py @@ -144,8 +144,15 @@ latex_mapping = { "c_uimm9sphi": "uimm[5]", "c_uimm10sp_s": "uimm[5:4$\\vert$9:6]", "c_uimm9sp_s": "uimm[5:3$\\vert$8:6]", + "rd_p_e": "rd\\,$'$, even values only", + "rs2_p_e": "rs2\\,$'$, even values only", + "rd_n0_e": "rd$\\neq$0, even values only", + "c_rs2_e": "rs2, even values only", + "rd_e": "rd, even values only", + "rs2_e": "rs2, even values only", } + # created a dummy instruction-dictionary like dictionary for all the instruction # types so that the same logic can be used to create their tables latex_inst_type = { @@ -44,8 +44,6 @@ 0xC21, "vtype" 0xC22, "vlenb" 0x100, "sstatus" -0x102, "sedeleg" -0x103, "sideleg" 0x104, "sie" 0x105, "stvec" 0x106, "scounteren" diff --git a/extensions/rv_i b/extensions/rv_i index 84f56c8..6d1fd38 100644 --- a/extensions/rv_i +++ b/extensions/rv_i @@ -50,7 +50,7 @@ $pseudo_op rv_i::ebreak sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x $pseudo_op rv_i::addi mv rd rs1 31..20=0 14..12=0 6..2=0x04 1..0=3 $pseudo_op rv_i::sub neg rd rs1 31..25=32 24..20=0x0 14..12=0 6..2=0x0C 1..0=3 $pseudo_op rv_i::addi nop 31..20=0 19..15=0 14..12=0 11..7=0 6..2=0x04 1..0=3 -$pseudo_op rv_i::andi zext.b rd rs1 31..20=0 14..12=7 6..2=0x04 1..0=3 +$pseudo_op rv_i::andi zext.b rd rs1 31..20=0xff 14..12=7 6..2=0x04 1..0=3 $pseudo_op rv_i::jalr ret 31..20=0 19..15=0x01 14..12=0 11..7=0 6..2=0x19 1..0=3 diff --git a/extensions/rv_zvkn b/extensions/rv_zvkn index 5a17e6d..ab38e15 100644 --- a/extensions/rv_zvkn +++ b/extensions/rv_zvkn @@ -1,9 +1,8 @@ # Zvkn, Vector Crypto Extension, NIST Algorithm Suite -# Import Zvbb +# Import Zvkb (proper subset of Zvbb extension) $import rv_zvbb::vandn.vv $import rv_zvbb::vandn.vx -$import rv_zvbb::vbrev.v $import rv_zvbb::vbrev8.v $import rv_zvbb::vrev8.v $import rv_zvbb::vrol.vv @@ -11,18 +10,6 @@ $import rv_zvbb::vrol.vx $import rv_zvbb::vror.vv $import rv_zvbb::vror.vx $import rv_zvbb::vror.vi -$import rv_zvbb::vclz.v -$import rv_zvbb::vctz.v -$import rv_zvbb::vcpop.v -$import rv_zvbb::vwsll.vv -$import rv_zvbb::vwsll.vx -$import rv_zvbb::vwsll.vi - -# Import Zvbc -$import rv_zvbc::vclmul.vv -$import rv_zvbc::vclmul.vx -$import rv_zvbc::vclmulh.vv -$import rv_zvbc::vclmulh.vx # Import Zvkned $import rv_zvkned::vaesef.vs diff --git a/extensions/rv_zvks b/extensions/rv_zvks index b5448bf..89626f7 100644 --- a/extensions/rv_zvks +++ b/extensions/rv_zvks @@ -1,9 +1,8 @@ # Zvk, Vector Crypto Extension, ShangMi Algorithm Suite -# Import Zvbb +# Import Zvkb (proper subset of the Zvbb extension) $import rv_zvbb::vandn.vv $import rv_zvbb::vandn.vx -$import rv_zvbb::vbrev.v $import rv_zvbb::vbrev8.v $import rv_zvbb::vrev8.v $import rv_zvbb::vrol.vv @@ -11,18 +10,6 @@ $import rv_zvbb::vrol.vx $import rv_zvbb::vror.vv $import rv_zvbb::vror.vx $import rv_zvbb::vror.vi -$import rv_zvbb::vclz.v -$import rv_zvbb::vctz.v -$import rv_zvbb::vcpop.v -$import rv_zvbb::vwsll.vv -$import rv_zvbb::vwsll.vx -$import rv_zvbb::vwsll.vi - -# Import Zvbc -$import rv_zvbc::vclmul.vv -$import rv_zvbc::vclmul.vx -$import rv_zvbc::vclmulh.vv -$import rv_zvbc::vclmulh.vx # Import Zvksed $import rv_zvksed::vsm4k.vi @@ -34,9 +34,10 @@ def generate_extensions( ): instr_dict = create_inst_dict(extensions, include_pseudo) instr_dict = dict(sorted(instr_dict.items())) + instr_dict_with_segment = add_segmented_vls_insn(instr_dict) with open("instr_dict.json", "w", encoding="utf-8") as outfile: - json.dump(add_segmented_vls_insn(instr_dict), outfile, indent=2) + json.dump(instr_dict_with_segment, outfile, indent=2) if c: instr_dict_c = create_inst_dict( @@ -63,7 +64,7 @@ def generate_extensions( logging.info("inst.rs generated successfully") if go: - make_go(instr_dict) + make_go(instr_dict_with_segment) logging.info("inst.go generated successfully") if latex: diff --git a/shared_utils.py b/shared_utils.py index f6cd4b7..9dd82e9 100644 --- a/shared_utils.py +++ b/shared_utils.py @@ -55,7 +55,7 @@ def validate_bit_range(msb: int, lsb: int, entry_value: int, line: str): # Split the instruction line into name and remaining part def parse_instruction_line(line: str) -> "tuple[str, str]": """Parse the instruction name and the remaining encoding details.""" - name, remaining = line.split(" ", 1) + name, remaining = line.replace("\t", " ").split(" ", 1) name = name.replace(".", "_") # Replace dots for compatibility remaining = remaining.lstrip() # Remove leading whitespace return name, remaining diff --git a/unratified/rv32_zclsd b/unratified/rv32_zclsd new file mode 100644 index 0000000..f8d7e82 --- /dev/null +++ b/unratified/rv32_zclsd @@ -0,0 +1,9 @@ +# Compressed load/store pair for RV32 + +# quadrant 0 +$pseudo_op rv32_c_f::c.flw c.ld rd_p_e rs1_p c_uimm8lo c_uimm8hi 2..0=0 15..13=3 +$pseudo_op rv32_c_f::c.fsw c.sd rs1_p rs2_p_e c_uimm8hi c_uimm8lo 2..0=0 15..13=7 + +#quadrant 2 +$pseudo_op rv32_c_f::c.flwsp c.ldsp rd_n0_e c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 7=0 +$pseudo_op rv32_c_f::c.fswsp c.sdsp c_rs2_e c_uimm9sp_s 2..0=2 15..13=7 diff --git a/unratified/rv32_zilsd b/unratified/rv32_zilsd new file mode 100644 index 0000000..ebf4281 --- /dev/null +++ b/unratified/rv32_zilsd @@ -0,0 +1,4 @@ +# Load/store pair for RV32 + +ld rd_e rs1 imm12 14..12=3 7..2=0x00 1..0=3 +sd imm12hi rs1 rs2_e imm12lo 20=0 14..12=3 6..2=0x08 1..0=3 |