diff options
| -rw-r--r-- | encoding.h | 11 | ||||
| -rwxr-xr-x | parse.py | 74 | ||||
| -rw-r--r-- | rv32_zicntr | 4 | ||||
| -rw-r--r-- | rv64_i | 2 | ||||
| -rw-r--r-- | rv_d | 7 | ||||
| -rw-r--r-- | rv_f | 15 | ||||
| -rw-r--r-- | rv_i | 29 | ||||
| -rw-r--r-- | rv_q | 7 | ||||
| -rw-r--r-- | rv_zfh | 5 | ||||
| -rw-r--r-- | rv_zicntr | 5 | ||||
| -rw-r--r-- | rv_zicsr | 26 |
11 files changed, 158 insertions, 27 deletions
@@ -214,6 +214,17 @@ #define MHPMEVENTH_MINH 0x40000000 #define MHPMEVENTH_OF 0x80000000 +#define MCOUNTEREN_CY_SHIFT 0 +#define MCOUNTEREN_TIME_SHIFT 1 +#define MCOUNTEREN_IR_SHIFT 2 + +#define MCOUNTEREN_CY (1U << MCOUNTEREN_CY_SHIFT) +#define MCOUNTEREN_TIME (1U << MCOUNTEREN_TIME_SHIFT) +#define MCOUNTEREN_IR (1U << MCOUNTEREN_IR_SHIFT) + +#define MCOUNTINHIBIT_CY MCOUNTEREN_CY +#define MCOUNTINHIBIT_IR MCOUNTEREN_IR + #define HENVCFG_FIOM 0x00000001 #define HENVCFG_LPE 0x00000004 #define HENVCFG_SSE 0x00000008 @@ -1,6 +1,7 @@ #!/usr/bin/env python3 from constants import * +import copy import re import glob import os @@ -112,16 +113,25 @@ def process_enc_line(line, ext): encoding_args = encoding.copy() for a in args: if a not in arg_lut: - logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') - raise SystemExit(1) - else: - (msb, lsb) = arg_lut[a] - for ind in range(lsb, msb + 1): - # overlapping bits - if encoding_args[31 - ind] != '-': - logging.error(f' Found variable {a} in instruction {name} overlapping {encoding_args[31 - ind]} variable in bit {ind}') + if len(parts := a.split('=')) == 2: + existing_arg, new_arg = parts + if existing_arg in arg_lut: + arg_lut[a] = arg_lut[existing_arg] + + else: + logging.error(f' Found field {existing_arg} in variable {a} in instruction {name} whose mapping in arg_lut does not exist') raise SystemExit(1) - encoding_args[31 - ind] = a + else: + logging.error(f' Found variable {a} in instruction {name} whose mapping in arg_lut does not exist') + raise SystemExit(1) + (msb, lsb) = arg_lut[a] + for ind in range(lsb, msb + 1): + # overlapping bits + if encoding_args[31 - ind] != '-': + logging.error(f' Found variable {a} in instruction {name} overlapping {encoding_args[31 - ind]} variable in bit {ind}') + raise SystemExit(1) + encoding_args[31 - ind] = a + # update the fields of the instruction as a dict and return back along with # the name of the instruction @@ -164,6 +174,37 @@ def extension_overlap_allowed(x, y): def instruction_overlap_allowed(x, y): return overlap_allowed(overlapping_instructions, x, y) +def add_segmented_vls_insn(instr_dict): + updated_dict = {} + for k, v in instr_dict.items(): + if "nf" in v['variable_fields']: + for new_key, new_value in expand_nf_field(k,v): + updated_dict[new_key] = new_value + else: + updated_dict[k] = v + return updated_dict + +def expand_nf_field(name, single_dict): + if "nf" not in single_dict['variable_fields']: + logging.error(f"Cannot expand nf field for instruction {name}") + raise SystemExit(1) + + # nf no longer a variable field + single_dict['variable_fields'].remove("nf") + # include nf in mask + single_dict['mask'] = hex(int(single_dict['mask'],16) | 0b111 << 29) + + name_expand_index = name.find('e') + expanded_instructions = [] + for nf in range(0,8): + new_single_dict = copy.deepcopy(single_dict) + new_single_dict['match'] = hex(int(single_dict['match'],16) | nf << 29) + new_single_dict['encoding'] = format(nf, '03b') + single_dict['encoding'][3:] + new_name = name if nf == 0 else name[:name_expand_index] + "seg" + str(nf+1) + name[name_expand_index:] + expanded_instructions.append((new_name, new_single_dict)) + return expanded_instructions + + def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]): ''' This function return a dictionary containing all instructions associated @@ -336,6 +377,18 @@ def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]): if name not in instr_dict: instr_dict[name] = single_dict logging.debug(f' including pseudo_ops:{name}') + else: + if(single_dict['match'] != instr_dict[name]['match']): + instr_dict[name + '_pseudo'] = single_dict + + # if a pseudo instruction has already been added to the filtered + # instruction dictionary but the extension is not in the current + # list, add it + else: + ext_name = single_dict['extension'] + + if (ext_name not in instr_dict[name]['extension']) & (name + '_pseudo' not in instr_dict): + instr_dict[name]['extension'].extend(ext_name) else: logging.debug(f' Skipping pseudo_op {pseudo_inst} since original instruction {orig_inst} already selected in list') @@ -1001,8 +1054,9 @@ if __name__ == "__main__": include_pseudo = True instr_dict = create_inst_dict(extensions, include_pseudo) + with open('instr_dict.yaml', 'w') as outfile: - yaml.dump(instr_dict, outfile, default_flow_style=False) + yaml.dump(add_segmented_vls_insn(instr_dict), outfile, default_flow_style=False) instr_dict = collections.OrderedDict(sorted(instr_dict.items())) if '-c' in sys.argv[1:]: diff --git a/rv32_zicntr b/rv32_zicntr new file mode 100644 index 0000000..2744bb2 --- /dev/null +++ b/rv32_zicntr @@ -0,0 +1,4 @@ +$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3
+
@@ -18,3 +18,5 @@ subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 + +$pseudo_op rv64_i::addiw sext.w rd rs1 31..20=0 14..12=0 6..2=0x06 1..0=3
\ No newline at end of file @@ -24,3 +24,10 @@ fcvt.w.d rd rs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 fcvt.d.w rd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 + +#pseudoinstructions +$pseudo_op rv_d::fsgnj.d fmv.d rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 +$pseudo_op rv_d::fsgnjx.d fabs.d rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 +$pseudo_op rv_d::fsgnjn.d fneg.d rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 + +
\ No newline at end of file @@ -29,3 +29,18 @@ fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 +#pseudointructions +$pseudo_op rv_f::fsgnj.s fmv.s rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fsgnjx.s fabs.s rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fsgnjn.s fneg.s rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 + +#CSRs +$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 + @@ -45,3 +45,32 @@ ebreak 31..20=0x001 19..7=0 6..2=0x1C 1..0=3 $pseudo_op rv_i::ecall scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 $pseudo_op rv_i::ebreak sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 + +#pseudoinstructions from asm manual +$pseudo_op rv_i::addi mv rd rs1 31..20=0 14..12=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::sub neg rd rs1 31..25=32 24..20=0x0 14..12=0 6..2=0x0C 1..0=3 +$pseudo_op rv_i::addi nop 31..20=0 19..15=0 14..12=0 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::andi zext.b rd rs1 31..20=0 14..12=7 6..2=0x04 1..0=3 + +$pseudo_op rv_i::jalr ret 31..20=0 19..15=0x01 14..12=0 11..7=0 6..2=0x19 1..0=3 + +$pseudo_op rv_i::bgeu bleu bimm12hi rs2 rs1 bimm12lo 14..12=7 6..2=0x18 1..0=3 +$pseudo_op rv_i::bltu bgtu bimm12hi rs2 rs1 bimm12lo 14..12=6 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge ble bimm12hi rs2 rs1 bimm12lo 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge bgez bimm12hi rs1 bimm12lo 24..20=0x0 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge blez bimm12hi rs2 bimm12lo 19..15=0x0 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bgt bimm12hi rs2 rs1 bimm12lo 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bgtz bimm12hi rs2 bimm12lo 19..15=0x0 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bltz bimm12hi rs1 bimm12lo 24..20=0x0 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::bne bnez bimm12hi rs1 bimm12lo 24..20=0x0 14..12=1 6..2=0x18 1..0=3 +$pseudo_op rv_i::beq beqz bimm12hi rs1 bimm12lo 24..20=0x0 14..12=0 6..2=0x18 1..0=3 + +$pseudo_op rv_i::sltiu seqz rd rs1 31..20=1 14..12=3 6..2=0x04 1..0=3 +$pseudo_op rv_i::sltu snez rd rs2 31..25=0 19..15=0x0 14..12=3 6..2=0x0C 1..0=3 +$pseudo_op rv_i::slt sltz rd rs1 31..25=0 24..20=0x0 14..12=2 6..2=0x0C 1..0=3 +$pseudo_op rv_i::slt sgtz rd rs2 31..25=0 19..15=0x0 14..12=2 6..2=0x0C 1..0=3 + +$pseudo_op rv_i::jalr jalr rs1 31..20=0 14..12=0 11..7=0x01 6..2=0x19 1..0=3 +$pseudo_op rv_i::jalr jr rs1 31..20=0 14..12=0 11..7=0x0 6..2=0x19 1..0=3 +$pseudo_op rv_i::jal jal jimm20 11..7=0x01 6..2=0x1b 1..0=3 +$pseudo_op rv_i::jal j jimm20 11..7=0x0 6..2=0x1b 1..0=3 @@ -26,3 +26,10 @@ fcvt.w.q rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 fcvt.wu.q rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 fcvt.q.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 fcvt.q.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 + + +#pseudoinstructions +$pseudo_op rv_q::fsgnj.q fmv.q rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 +$pseudo_op rv_q::fsgnjx.q fabs.q rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 +$pseudo_op rv_q::fsgnjn.q fneg.q rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 + @@ -28,3 +28,8 @@ fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 +#pseudoinstructions +$pseudo_op rv_zfh::fsgnj.h fmv.h rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +$pseudo_op rv_zfh::fsgnjx.h fabs.h rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +$pseudo_op rv_zfh::fsgnjn.h fneg.h rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 + diff --git a/rv_zicntr b/rv_zicntr new file mode 100644 index 0000000..deecaa0 --- /dev/null +++ b/rv_zicntr @@ -0,0 +1,5 @@ +#rv_zicntr instructions
+$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3
+
@@ -1,23 +1,15 @@ -csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 +csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 csrrs rd rs1 csr 14..12=2 6..2=0x1C 1..0=3 csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 - - +#pseudoinstructions +$pseudo_op rv_zicsr::csrrs csrr rd csr 19..15=0x0 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw csrw rs1 csr 14..12=1 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs csrs rs1 csr 14..12=2 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrc csrc rs1 csr 14..12=3 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi csrwi csr zimm 14..12=5 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrsi csrsi csr zimm 14..12=6 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrci csrci csr zimm 14..12=7 11..7=0x0 6..2=0x1C 1..0=3 |