diff options
| -rw-r--r-- | inst.v | 567 | ||||
| -rw-r--r-- | instr-table.tex | 1329 | ||||
| -rw-r--r-- | opcodes | 52 | ||||
| -rwxr-xr-x | parse-opcodes | 387 |
4 files changed, 924 insertions, 1411 deletions
@@ -1,286 +1,283 @@ /* Automatically generated by parse-opcodes */ -`define J 32'b?????????????????????????_1100111 -`define JAL 32'b?????????????????????????_1101111 -`define JALR_C 32'b?????_?????_????????????_000_1101011 -`define JALR_R 32'b?????_?????_????????????_001_1101011 -`define JALR_J 32'b?????_?????_????????????_010_1101011 -`define BEQ 32'b?????_?????_?????_???????_000_1100011 -`define BNE 32'b?????_?????_?????_???????_001_1100011 -`define BLT 32'b?????_?????_?????_???????_100_1100011 -`define BGE 32'b?????_?????_?????_???????_101_1100011 -`define BLTU 32'b?????_?????_?????_???????_110_1100011 -`define BGEU 32'b?????_?????_?????_???????_111_1100011 -`define LUI 32'b?????_????????????????????_0110111 -`define AUIPC 32'b?????_????????????????????_0010111 -`define ADDI 32'b?????_?????_????????????_000_0010011 -`define SLLI 32'b?????_?????_000000_??????_001_0010011 -`define SLTI 32'b?????_?????_????????????_010_0010011 -`define SLTIU 32'b?????_?????_????????????_011_0010011 -`define XORI 32'b?????_?????_????????????_100_0010011 -`define SRLI 32'b?????_?????_000000_??????_101_0010011 -`define SRAI 32'b?????_?????_000001_??????_101_0010011 -`define ORI 32'b?????_?????_????????????_110_0010011 -`define ANDI 32'b?????_?????_????????????_111_0010011 -`define ADD 32'b?????_?????_?????_0000000000_0110011 -`define SUB 32'b?????_?????_?????_1000000000_0110011 -`define SLL 32'b?????_?????_?????_0000000001_0110011 -`define SLT 32'b?????_?????_?????_0000000010_0110011 -`define SLTU 32'b?????_?????_?????_0000000011_0110011 -`define XOR 32'b?????_?????_?????_0000000100_0110011 -`define SRL 32'b?????_?????_?????_0000000101_0110011 -`define SRA 32'b?????_?????_?????_1000000101_0110011 -`define OR 32'b?????_?????_?????_0000000110_0110011 -`define AND 32'b?????_?????_?????_0000000111_0110011 -`define MUL 32'b?????_?????_?????_0000001000_0110011 -`define MULH 32'b?????_?????_?????_0000001001_0110011 -`define MULHSU 32'b?????_?????_?????_0000001010_0110011 -`define MULHU 32'b?????_?????_?????_0000001011_0110011 -`define DIV 32'b?????_?????_?????_0000001100_0110011 -`define DIVU 32'b?????_?????_?????_0000001101_0110011 -`define REM 32'b?????_?????_?????_0000001110_0110011 -`define REMU 32'b?????_?????_?????_0000001111_0110011 -`define ADDIW 32'b?????_?????_????????????_000_0011011 -`define SLLIW 32'b?????_?????_000000_0_?????_001_0011011 -`define SRLIW 32'b?????_?????_000000_0_?????_101_0011011 -`define SRAIW 32'b?????_?????_000001_0_?????_101_0011011 -`define ADDW 32'b?????_?????_?????_0000000000_0111011 -`define SUBW 32'b?????_?????_?????_1000000000_0111011 -`define SLLW 32'b?????_?????_?????_0000000001_0111011 -`define SRLW 32'b?????_?????_?????_0000000101_0111011 -`define SRAW 32'b?????_?????_?????_1000000101_0111011 -`define MULW 32'b?????_?????_?????_0000001000_0111011 -`define DIVW 32'b?????_?????_?????_0000001100_0111011 -`define DIVUW 32'b?????_?????_?????_0000001101_0111011 -`define REMW 32'b?????_?????_?????_0000001110_0111011 -`define REMUW 32'b?????_?????_?????_0000001111_0111011 -`define LB 32'b?????_?????_????????????_000_0000011 -`define LH 32'b?????_?????_????????????_001_0000011 -`define LW 32'b?????_?????_????????????_010_0000011 -`define LD 32'b?????_?????_????????????_011_0000011 -`define LBU 32'b?????_?????_????????????_100_0000011 -`define LHU 32'b?????_?????_????????????_101_0000011 -`define LWU 32'b?????_?????_????????????_110_0000011 -`define SB 32'b?????_?????_?????_???????_000_0100011 -`define SH 32'b?????_?????_?????_???????_001_0100011 -`define SW 32'b?????_?????_?????_???????_010_0100011 -`define SD 32'b?????_?????_?????_???????_011_0100011 -`define AMOADD_W 32'b?????_?????_?????_0000000010_0101011 -`define AMOSWAP_W 32'b?????_?????_?????_0000001010_0101011 -`define AMOAND_W 32'b?????_?????_?????_0000010010_0101011 -`define AMOOR_W 32'b?????_?????_?????_0000011010_0101011 -`define AMOMIN_W 32'b?????_?????_?????_0000100010_0101011 -`define AMOMAX_W 32'b?????_?????_?????_0000101010_0101011 -`define AMOMINU_W 32'b?????_?????_?????_0000110010_0101011 -`define AMOMAXU_W 32'b?????_?????_?????_0000111010_0101011 -`define AMOADD_D 32'b?????_?????_?????_0000000011_0101011 -`define AMOSWAP_D 32'b?????_?????_?????_0000001011_0101011 -`define AMOAND_D 32'b?????_?????_?????_0000010011_0101011 -`define AMOOR_D 32'b?????_?????_?????_0000011011_0101011 -`define AMOMIN_D 32'b?????_?????_?????_0000100011_0101011 -`define AMOMAX_D 32'b?????_?????_?????_0000101011_0101011 -`define AMOMINU_D 32'b?????_?????_?????_0000110011_0101011 -`define AMOMAXU_D 32'b?????_?????_?????_0000111011_0101011 -`define LR_W 32'b?????_?????_00000_1000000010_0101011 -`define LR_D 32'b?????_?????_00000_1000000011_0101011 -`define SC_W 32'b?????_?????_?????_1000001010_0101011 -`define SC_D 32'b?????_?????_?????_1000001011_0101011 -`define FENCE_I 32'b?????_?????_????????????_001_0101111 -`define FENCE 32'b?????_?????_????????????_010_0101111 -`define FENCE_V_L 32'b?????_?????_????????????_100_0101111 -`define FENCE_V_G 32'b?????_?????_????????????_101_0101111 -`define SYSCALL 32'b00000_00000_00000_0000000000_1110111 -`define BREAK 32'b00000_00000_00000_0000000001_1110111 -`define RDCYCLE 32'b?????_00000_00000_0000000100_1110111 -`define RDTIME 32'b?????_00000_00000_0000001100_1110111 -`define RDINSTRET 32'b?????_00000_00000_0000010100_1110111 -`define STOP 32'b00000_00000_00000_0000000010_1110111 -`define UTIDX 32'b?????_00000_00000_0000000011_1110111 -`define MOVZ 32'b?????_?????_?????_0000000101_1110111 -`define MOVN 32'b?????_?????_?????_0000001101_1110111 -`define FMOVZ 32'b?????_?????_?????_0000010101_1110111 -`define FMOVN 32'b?????_?????_?????_0000011101_1110111 -`define CLEARPCR 32'b?????_?????_????????????_000_1111011 -`define SETPCR 32'b?????_?????_????????????_001_1111011 -`define MFPCR 32'b?????_?????_00000_0000000010_1111011 -`define MTPCR 32'b?????_?????_?????_0000000011_1111011 -`define ERET 32'b00000_00000_00000_0000000100_1111011 -`define CFLUSH 32'b00000_00000_00000_0000000101_1111011 -`define VXCPTSAVE 32'b00000_?????_00000_0000000110_1111011 -`define VXCPTRESTORE 32'b00000_?????_00000_0000001110_1111011 -`define VXCPTKILL 32'b00000_00000_00000_0000010110_1111011 -`define VXCPTEVAC 32'b00000_?????_00000_0001000110_1111011 -`define VXCPTHOLD 32'b00000_00000_00000_0001001110_1111011 -`define VENQCMD 32'b00000_?????_?????_0001010110_1111011 -`define VENQIMM1 32'b00000_?????_?????_0001011110_1111011 -`define VENQIMM2 32'b00000_?????_?????_0001100110_1111011 -`define VENQCNT 32'b00000_?????_?????_0001101110_1111011 -`define FADD_S 32'b?????_?????_?????_00000_???_00_1010011 -`define FSUB_S 32'b?????_?????_?????_00001_???_00_1010011 -`define FMUL_S 32'b?????_?????_?????_00010_???_00_1010011 -`define FDIV_S 32'b?????_?????_?????_00011_???_00_1010011 -`define FSQRT_S 32'b?????_?????_00000_00100_???_00_1010011 -`define FSGNJ_S 32'b?????_?????_?????_00101_000_00_1010011 -`define FSGNJN_S 32'b?????_?????_?????_00110_000_00_1010011 -`define FSGNJX_S 32'b?????_?????_?????_00111_000_00_1010011 -`define FADD_D 32'b?????_?????_?????_00000_???_01_1010011 -`define FSUB_D 32'b?????_?????_?????_00001_???_01_1010011 -`define FMUL_D 32'b?????_?????_?????_00010_???_01_1010011 -`define FDIV_D 32'b?????_?????_?????_00011_???_01_1010011 -`define FSQRT_D 32'b?????_?????_00000_00100_???_01_1010011 -`define FSGNJ_D 32'b?????_?????_?????_00101_000_01_1010011 -`define FSGNJN_D 32'b?????_?????_?????_00110_000_01_1010011 -`define FSGNJX_D 32'b?????_?????_?????_00111_000_01_1010011 -`define FCVT_L_S 32'b?????_?????_00000_01000_???_00_1010011 -`define FCVT_LU_S 32'b?????_?????_00000_01001_???_00_1010011 -`define FCVT_W_S 32'b?????_?????_00000_01010_???_00_1010011 -`define FCVT_WU_S 32'b?????_?????_00000_01011_???_00_1010011 -`define FCVT_L_D 32'b?????_?????_00000_01000_???_01_1010011 -`define FCVT_LU_D 32'b?????_?????_00000_01001_???_01_1010011 -`define FCVT_W_D 32'b?????_?????_00000_01010_???_01_1010011 -`define FCVT_WU_D 32'b?????_?????_00000_01011_???_01_1010011 -`define FCVT_S_L 32'b?????_?????_00000_01100_???_00_1010011 -`define FCVT_S_LU 32'b?????_?????_00000_01101_???_00_1010011 -`define FCVT_S_W 32'b?????_?????_00000_01110_???_00_1010011 -`define FCVT_S_WU 32'b?????_?????_00000_01111_???_00_1010011 -`define FCVT_D_L 32'b?????_?????_00000_01100_???_01_1010011 -`define FCVT_D_LU 32'b?????_?????_00000_01101_???_01_1010011 -`define FCVT_D_W 32'b?????_?????_00000_01110_???_01_1010011 -`define FCVT_D_WU 32'b?????_?????_00000_01111_???_01_1010011 -`define FCVT_S_D 32'b?????_?????_00000_10001_???_00_1010011 -`define FCVT_D_S 32'b?????_?????_00000_10000_???_01_1010011 -`define FEQ_S 32'b?????_?????_?????_10101_000_00_1010011 -`define FLT_S 32'b?????_?????_?????_10110_000_00_1010011 -`define FLE_S 32'b?????_?????_?????_10111_000_00_1010011 -`define FEQ_D 32'b?????_?????_?????_10101_000_01_1010011 -`define FLT_D 32'b?????_?????_?????_10110_000_01_1010011 -`define FLE_D 32'b?????_?????_?????_10111_000_01_1010011 -`define FMIN_S 32'b?????_?????_?????_11000_000_00_1010011 -`define FMAX_S 32'b?????_?????_?????_11001_000_00_1010011 -`define FMIN_D 32'b?????_?????_?????_11000_000_01_1010011 -`define FMAX_D 32'b?????_?????_?????_11001_000_01_1010011 -`define MFTX_S 32'b?????_?????_00000_11100_000_00_1010011 -`define MFTX_D 32'b?????_?????_00000_11100_000_01_1010011 -`define MFFSR 32'b?????_00000_00000_11101_000_00_1010011 -`define MXTF_S 32'b?????_?????_00000_11110_000_00_1010011 -`define MXTF_D 32'b?????_?????_00000_11110_000_01_1010011 -`define MTFSR 32'b?????_?????_00000_11111_000_00_1010011 -`define FLW 32'b?????_?????_????????????_010_0000111 -`define FLD 32'b?????_?????_????????????_011_0000111 -`define FSW 32'b?????_?????_?????_???????_010_0100111 -`define FSD 32'b?????_?????_?????_???????_011_0100111 -`define FMADD_S 32'b?????_?????_?????_?????_???_00_1000011 -`define FMSUB_S 32'b?????_?????_?????_?????_???_00_1000111 -`define FNMSUB_S 32'b?????_?????_?????_?????_???_00_1001011 -`define FNMADD_S 32'b?????_?????_?????_?????_???_00_1001111 -`define FMADD_D 32'b?????_?????_?????_?????_???_01_1000011 -`define FMSUB_D 32'b?????_?????_?????_?????_???_01_1000111 -`define FNMSUB_D 32'b?????_?????_?????_?????_???_01_1001011 -`define FNMADD_D 32'b?????_?????_?????_?????_???_01_1001111 -`define VLD 32'b?????_?????_00000_0000000011_0001011 -`define VLW 32'b?????_?????_00000_0000000010_0001011 -`define VLWU 32'b?????_?????_00000_0000000110_0001011 -`define VLH 32'b?????_?????_00000_0000000001_0001011 -`define VLHU 32'b?????_?????_00000_0000000101_0001011 -`define VLB 32'b?????_?????_00000_0000000000_0001011 -`define VLBU 32'b?????_?????_00000_0000000100_0001011 -`define VFLD 32'b?????_?????_00000_0000001011_0001011 -`define VFLW 32'b?????_?????_00000_0000001010_0001011 -`define VLSTD 32'b?????_?????_?????_0000100011_0001011 -`define VLSTW 32'b?????_?????_?????_0000100010_0001011 -`define VLSTWU 32'b?????_?????_?????_0000100110_0001011 -`define VLSTH 32'b?????_?????_?????_0000100001_0001011 -`define VLSTHU 32'b?????_?????_?????_0000100101_0001011 -`define VLSTB 32'b?????_?????_?????_0000100000_0001011 -`define VLSTBU 32'b?????_?????_?????_0000100100_0001011 -`define VFLSTD 32'b?????_?????_?????_0000101011_0001011 -`define VFLSTW 32'b?????_?????_?????_0000101010_0001011 -`define VLSEGD 32'b?????_?????_?????_0001000011_0001011 -`define VLSEGW 32'b?????_?????_?????_0001000010_0001011 -`define VLSEGWU 32'b?????_?????_?????_0001000110_0001011 -`define VLSEGH 32'b?????_?????_?????_0001000001_0001011 -`define VLSEGHU 32'b?????_?????_?????_0001000101_0001011 -`define VLSEGB 32'b?????_?????_?????_0001000000_0001011 -`define VLSEGBU 32'b?????_?????_?????_0001000100_0001011 -`define VFLSEGD 32'b?????_?????_?????_0001001011_0001011 -`define VFLSEGW 32'b?????_?????_?????_0001001010_0001011 -`define VLSEGSTD 32'b?????_?????_?????_?????_100_11_0001011 -`define VLSEGSTW 32'b?????_?????_?????_?????_100_10_0001011 -`define VLSEGSTWU 32'b?????_?????_?????_?????_101_10_0001011 -`define VLSEGSTH 32'b?????_?????_?????_?????_100_01_0001011 -`define VLSEGSTHU 32'b?????_?????_?????_?????_101_01_0001011 -`define VLSEGSTB 32'b?????_?????_?????_?????_100_00_0001011 -`define VLSEGSTBU 32'b?????_?????_?????_?????_101_00_0001011 -`define VFLSEGSTD 32'b?????_?????_?????_?????_110_11_0001011 -`define VFLSEGSTW 32'b?????_?????_?????_?????_110_10_0001011 -`define VSD 32'b?????_?????_00000_0000000011_0001111 -`define VSW 32'b?????_?????_00000_0000000010_0001111 -`define VSH 32'b?????_?????_00000_0000000001_0001111 -`define VSB 32'b?????_?????_00000_0000000000_0001111 -`define VFSD 32'b?????_?????_00000_0000001011_0001111 -`define VFSW 32'b?????_?????_00000_0000001010_0001111 -`define VSSTD 32'b?????_?????_?????_0000100011_0001111 -`define VSSTW 32'b?????_?????_?????_0000100010_0001111 -`define VSSTH 32'b?????_?????_?????_0000100001_0001111 -`define VSSTB 32'b?????_?????_?????_0000100000_0001111 -`define VFSSTD 32'b?????_?????_?????_0000101011_0001111 -`define VFSSTW 32'b?????_?????_?????_0000101010_0001111 -`define VSSEGD 32'b?????_?????_?????_0001000011_0001111 -`define VSSEGW 32'b?????_?????_?????_0001000010_0001111 -`define VSSEGH 32'b?????_?????_?????_0001000001_0001111 -`define VSSEGB 32'b?????_?????_?????_0001000000_0001111 -`define VFSSEGD 32'b?????_?????_?????_0001001011_0001111 -`define VFSSEGW 32'b?????_?????_?????_0001001010_0001111 -`define VSSEGSTD 32'b?????_?????_?????_?????_100_11_0001111 -`define VSSEGSTW 32'b?????_?????_?????_?????_100_10_0001111 -`define VSSEGSTH 32'b?????_?????_?????_?????_100_01_0001111 -`define VSSEGSTB 32'b?????_?????_?????_?????_100_00_0001111 -`define VFSSEGSTD 32'b?????_?????_?????_?????_110_11_0001111 -`define VFSSEGSTW 32'b?????_?????_?????_?????_110_10_0001111 -`define VMVV 32'b?????_?????_00000_0000000000_1110011 -`define VMSV 32'b?????_?????_00000_0000010000_1110011 -`define VMST 32'b?????_?????_?????_0000100000_1110011 -`define VMTS 32'b?????_?????_?????_0000110000_1110011 -`define VFMVV 32'b?????_?????_00000_0000000010_1110011 -`define VFMSV 32'b?????_?????_00000_0000010010_1110011 -`define VFMST 32'b?????_?????_?????_0000100010_1110011 -`define VFMTS 32'b?????_?????_?????_0000110010_1110011 -`define VVCFG 32'b00000_?????_?????_0000001000_1110011 -`define VTCFG 32'b00000_?????_?????_0000011000_1110011 -`define VVCFGIVL 32'b?????_?????_????????????_001_1110011 -`define VTCFGIVL 32'b?????_?????_????????????_011_1110011 -`define VSETVL 32'b?????_?????_000000000000_101_1110011 -`define VF 32'b00000_?????_????????????_111_1110011 -`define C_LI 32'b00000000000000000000000000000000 -`define C_ADDI 32'b00000000000000000000000000000000 -`define C_ADDIW 32'b00000000000000000000000000000000 -`define C_LDSP 32'b00000000000000000000000000000000 -`define C_LWSP 32'b00000000000000000000000000000000 -`define C_SDSP 32'b00000000000000000000000000000000 -`define C_SWSP 32'b00000000000000000000000000000000 -`define C_LW0 32'b00000000000000000000000000000000 -`define C_LD0 32'b00000000000000000000000000000000 -`define C_ADD 32'b00000000000000000000000000000000 -`define C_SUB 32'b00000000000000000000000000000000 -`define C_MOVE 32'b00000000000000000000000000000000 -`define C_J 32'b00000000000000000000000000000000 -`define C_LD 32'b00000000000000000000000000000000 -`define C_LW 32'b00000000000000000000000000000000 -`define C_SD 32'b00000000000000000000000000000000 -`define C_SW 32'b00000000000000000000000000000000 -`define C_BEQ 32'b00000000000000000000000000000000 -`define C_BNE 32'b00000000000000000000000000000000 -`define C_FLW 32'b00000000000000000000000000000000 -`define C_FLD 32'b00000000000000000000000000000000 -`define C_FSW 32'b00000000000000000000000000000000 -`define C_FSD 32'b00000000000000000000000000000000 -`define C_SLLI 32'b00000000000000000000000000000000 -`define C_SLLI32 32'b00000000000000000000000000000000 -`define C_SRLI 32'b00000000000000000000000000000000 -`define C_SRLI32 32'b00000000000000000000000000000000 -`define C_SRAI 32'b00000000000000000000000000000000 -`define C_SRAI32 32'b00000000000000000000000000000000 -`define C_SLLIW 32'b00000000000000000000000000000000 -`define C_ADD3 32'b00000000000000000000000000000000 -`define C_SUB3 32'b00000000000000000000000000000000 -`define C_OR3 32'b00000000000000000000000000000000 -`define C_AND3 32'b00000000000000000000000000000000 +`define J 32'b?????????????????????????1100111 +`define JAL 32'b?????????????????????????1101111 +`define JALR 32'b??????????????????????0001101011 +`define BEQ 32'b??????????????????????0001100011 +`define BNE 32'b??????????????????????0011100011 +`define BLT 32'b??????????????????????1001100011 +`define BGE 32'b??????????????????????1011100011 +`define BLTU 32'b??????????????????????1101100011 +`define BGEU 32'b??????????????????????1111100011 +`define LUI 32'b?????????????????????????0110111 +`define AUIPC 32'b?????????????????????????0010111 +`define ADDI 32'b??????????????????????0000010011 +`define SLLI 32'b??????????000000??????0010010011 +`define SLTI 32'b??????????????????????0100010011 +`define SLTIU 32'b??????????????????????0110010011 +`define XORI 32'b??????????????????????1000010011 +`define SRLI 32'b??????????000000??????1010010011 +`define SRAI 32'b??????????000001??????1010010011 +`define ORI 32'b??????????????????????1100010011 +`define ANDI 32'b??????????????????????1110010011 +`define ADD 32'b???????????????00000000000110011 +`define SUB 32'b???????????????10000000000110011 +`define SLL 32'b???????????????00000000010110011 +`define SLT 32'b???????????????00000000100110011 +`define SLTU 32'b???????????????00000000110110011 +`define XOR 32'b???????????????00000001000110011 +`define SRL 32'b???????????????00000001010110011 +`define SRA 32'b???????????????10000001010110011 +`define OR 32'b???????????????00000001100110011 +`define AND 32'b???????????????00000001110110011 +`define MUL 32'b???????????????00000010000110011 +`define MULH 32'b???????????????00000010010110011 +`define MULHSU 32'b???????????????00000010100110011 +`define MULHU 32'b???????????????00000010110110011 +`define DIV 32'b???????????????00000011000110011 +`define DIVU 32'b???????????????00000011010110011 +`define REM 32'b???????????????00000011100110011 +`define REMU 32'b???????????????00000011110110011 +`define ADDIW 32'b??????????????????????0000011011 +`define SLLIW 32'b??????????0000000?????0010011011 +`define SRLIW 32'b??????????0000000?????1010011011 +`define SRAIW 32'b??????????0000010?????1010011011 +`define ADDW 32'b???????????????00000000000111011 +`define SUBW 32'b???????????????10000000000111011 +`define SLLW 32'b???????????????00000000010111011 +`define SRLW 32'b???????????????00000001010111011 +`define SRAW 32'b???????????????10000001010111011 +`define MULW 32'b???????????????00000010000111011 +`define DIVW 32'b???????????????00000011000111011 +`define DIVUW 32'b???????????????00000011010111011 +`define REMW 32'b???????????????00000011100111011 +`define REMUW 32'b???????????????00000011110111011 +`define LB 32'b??????????????????????0000000011 +`define LH 32'b??????????????????????0010000011 +`define LW 32'b??????????????????????0100000011 +`define LD 32'b??????????????????????0110000011 +`define LBU 32'b??????????????????????1000000011 +`define LHU 32'b??????????????????????1010000011 +`define LWU 32'b??????????????????????1100000011 +`define SB 32'b??????????????????????0000100011 +`define SH 32'b??????????????????????0010100011 +`define SW 32'b??????????????????????0100100011 +`define SD 32'b??????????????????????0110100011 +`define AMOADD_W 32'b???????????????00000000100101011 +`define AMOSWAP_W 32'b???????????????00000010100101011 +`define AMOAND_W 32'b???????????????00000100100101011 +`define AMOOR_W 32'b???????????????00000110100101011 +`define AMOMIN_W 32'b???????????????00001000100101011 +`define AMOMAX_W 32'b???????????????00001010100101011 +`define AMOMINU_W 32'b???????????????00001100100101011 +`define AMOMAXU_W 32'b???????????????00001110100101011 +`define AMOADD_D 32'b???????????????00000000110101011 +`define AMOSWAP_D 32'b???????????????00000010110101011 +`define AMOAND_D 32'b???????????????00000100110101011 +`define AMOOR_D 32'b???????????????00000110110101011 +`define AMOMIN_D 32'b???????????????00001000110101011 +`define AMOMAX_D 32'b???????????????00001010110101011 +`define AMOMINU_D 32'b???????????????00001100110101011 +`define AMOMAXU_D 32'b???????????????00001110110101011 +`define LR_W 32'b??????????0000010000000100101011 +`define LR_D 32'b??????????0000010000000110101011 +`define SC_W 32'b???????????????10000010100101011 +`define SC_D 32'b???????????????10000010110101011 +`define FENCE_I 32'b??????????????????????0010101111 +`define FENCE 32'b??????????????????????0100101111 +`define FENCE_V_L 32'b??????????????????????1000101111 +`define FENCE_V_G 32'b??????????????????????1010101111 +`define SYSCALL 32'b00000000000000000000000001110111 +`define BREAK 32'b00000000000000000000000011110111 +`define RDCYCLE 32'b?????000000000000000001001110111 +`define RDTIME 32'b?????000000000000000011001110111 +`define RDINSTRET 32'b?????000000000000000101001110111 +`define CLEARPCR 32'b??????????????????????0001111011 +`define SETPCR 32'b??????????????????????0011111011 +`define MFPCR 32'b??????????0000000000000101111011 +`define MTPCR 32'b???????????????00000000111111011 +`define ERET 32'b00000000000000000000001001111011 +`define FADD_S 32'b???????????????00000???001010011 +`define FSUB_S 32'b???????????????00001???001010011 +`define FMUL_S 32'b???????????????00010???001010011 +`define FDIV_S 32'b???????????????00011???001010011 +`define FSQRT_S 32'b??????????0000000100???001010011 +`define FSGNJ_S 32'b???????????????00101000001010011 +`define FSGNJN_S 32'b???????????????00110000001010011 +`define FSGNJX_S 32'b???????????????00111000001010011 +`define FADD_D 32'b???????????????00000???011010011 +`define FSUB_D 32'b???????????????00001???011010011 +`define FMUL_D 32'b???????????????00010???011010011 +`define FDIV_D 32'b???????????????00011???011010011 +`define FSQRT_D 32'b??????????0000000100???011010011 +`define FSGNJ_D 32'b???????????????00101000011010011 +`define FSGNJN_D 32'b???????????????00110000011010011 +`define FSGNJX_D 32'b???????????????00111000011010011 +`define FCVT_L_S 32'b??????????0000001000???001010011 +`define FCVT_LU_S 32'b??????????0000001001???001010011 +`define FCVT_W_S 32'b??????????0000001010???001010011 +`define FCVT_WU_S 32'b??????????0000001011???001010011 +`define FCVT_L_D 32'b??????????0000001000???011010011 +`define FCVT_LU_D 32'b??????????0000001001???011010011 +`define FCVT_W_D 32'b??????????0000001010???011010011 +`define FCVT_WU_D 32'b??????????0000001011???011010011 +`define FCVT_S_L 32'b??????????0000001100???001010011 +`define FCVT_S_LU 32'b??????????0000001101???001010011 +`define FCVT_S_W 32'b??????????0000001110???001010011 +`define FCVT_S_WU 32'b??????????0000001111???001010011 +`define FCVT_D_L 32'b??????????0000001100???011010011 +`define FCVT_D_LU 32'b??????????0000001101???011010011 +`define FCVT_D_W 32'b??????????0000001110???011010011 +`define FCVT_D_WU 32'b??????????0000001111???011010011 +`define FCVT_S_D 32'b??????????0000010001???001010011 +`define FCVT_D_S 32'b??????????0000010000???011010011 +`define FEQ_S 32'b???????????????10101000001010011 +`define FLT_S 32'b???????????????10110000001010011 +`define FLE_S 32'b???????????????10111000001010011 +`define FEQ_D 32'b???????????????10101000011010011 +`define FLT_D 32'b???????????????10110000011010011 +`define FLE_D 32'b???????????????10111000011010011 +`define FMIN_S 32'b???????????????11000000001010011 +`define FMAX_S 32'b???????????????11001000001010011 +`define FMIN_D 32'b???????????????11000000011010011 +`define FMAX_D 32'b???????????????11001000011010011 +`define MFTX_S 32'b??????????0000011100000001010011 +`define MFTX_D 32'b??????????0000011100000011010011 +`define MFFSR 32'b?????000000000011101000001010011 +`define MXTF_S 32'b??????????0000011110000001010011 +`define MXTF_D 32'b??????????0000011110000011010011 +`define MTFSR 32'b??????????0000011111000001010011 +`define FLW 32'b??????????????????????0100000111 +`define FLD 32'b??????????????????????0110000111 +`define FSW 32'b??????????????????????0100100111 +`define FSD 32'b??????????????????????0110100111 +`define FMADD_S 32'b???????????????????????001000011 +`define FMSUB_S 32'b???????????????????????001000111 +`define FNMSUB_S 32'b???????????????????????001001011 +`define FNMADD_S 32'b???????????????????????001001111 +`define FMADD_D 32'b???????????????????????011000011 +`define FMSUB_D 32'b???????????????????????011000111 +`define FNMSUB_D 32'b???????????????????????011001011 +`define FNMADD_D 32'b???????????????????????011001111 +`define STOP 32'b00000000000000000000000101110111 +`define UTIDX 32'b?????000000000000000000111110111 +`define MOVZ 32'b???????????????00000001011110111 +`define MOVN 32'b???????????????00000011011110111 +`define FMOVZ 32'b???????????????00000101011110111 +`define FMOVN 32'b???????????????00000111011110111 +`define VXCPTSAVE 32'b00000?????0000000000001101111011 +`define VXCPTRESTORE 32'b00000?????0000000000011101111011 +`define VXCPTKILL 32'b00000000000000000000101101111011 +`define VXCPTEVAC 32'b00000?????0000000010001101111011 +`define VXCPTHOLD 32'b00000000000000000010011101111011 +`define VENQCMD 32'b00000??????????00010101101111011 +`define VENQIMM1 32'b00000??????????00010111101111011 +`define VENQIMM2 32'b00000??????????00011001101111011 +`define VENQCNT 32'b00000??????????00011011101111011 +`define VLD 32'b??????????0000000000000110001011 +`define VLW 32'b??????????0000000000000100001011 +`define VLWU 32'b??????????0000000000001100001011 +`define VLH 32'b??????????0000000000000010001011 +`define VLHU 32'b??????????0000000000001010001011 +`define VLB 32'b??????????0000000000000000001011 +`define VLBU 32'b??????????0000000000001000001011 +`define VFLD 32'b??????????0000000000010110001011 +`define VFLW 32'b??????????0000000000010100001011 +`define VLSTD 32'b???????????????00001000110001011 +`define VLSTW 32'b???????????????00001000100001011 +`define VLSTWU 32'b???????????????00001001100001011 +`define VLSTH 32'b???????????????00001000010001011 +`define VLSTHU 32'b???????????????00001001010001011 +`define VLSTB 32'b???????????????00001000000001011 +`define VLSTBU 32'b???????????????00001001000001011 +`define VFLSTD 32'b???????????????00001010110001011 +`define VFLSTW 32'b???????????????00001010100001011 +`define VLSEGD 32'b???????????????00010000110001011 +`define VLSEGW 32'b???????????????00010000100001011 +`define VLSEGWU 32'b???????????????00010001100001011 +`define VLSEGH 32'b???????????????00010000010001011 +`define VLSEGHU 32'b???????????????00010001010001011 +`define VLSEGB 32'b???????????????00010000000001011 +`define VLSEGBU 32'b???????????????00010001000001011 +`define VFLSEGD 32'b???????????????00010010110001011 +`define VFLSEGW 32'b???????????????00010010100001011 +`define VLSEGSTD 32'b????????????????????100110001011 +`define VLSEGSTW 32'b????????????????????100100001011 +`define VLSEGSTWU 32'b????????????????????101100001011 +`define VLSEGSTH 32'b????????????????????100010001011 +`define VLSEGSTHU 32'b????????????????????101010001011 +`define VLSEGSTB 32'b????????????????????100000001011 +`define VLSEGSTBU 32'b????????????????????101000001011 +`define VFLSEGSTD 32'b????????????????????110110001011 +`define VFLSEGSTW 32'b????????????????????110100001011 +`define VSD 32'b??????????0000000000000110001111 +`define VSW 32'b??????????0000000000000100001111 +`define VSH 32'b??????????0000000000000010001111 +`define VSB 32'b??????????0000000000000000001111 +`define VFSD 32'b??????????0000000000010110001111 +`define VFSW 32'b??????????0000000000010100001111 +`define VSSTD 32'b???????????????00001000110001111 +`define VSSTW 32'b???????????????00001000100001111 +`define VSSTH 32'b???????????????00001000010001111 +`define VSSTB 32'b???????????????00001000000001111 +`define VFSSTD 32'b???????????????00001010110001111 +`define VFSSTW 32'b???????????????00001010100001111 +`define VSSEGD 32'b???????????????00010000110001111 +`define VSSEGW 32'b???????????????00010000100001111 +`define VSSEGH 32'b???????????????00010000010001111 +`define VSSEGB 32'b???????????????00010000000001111 +`define VFSSEGD 32'b???????????????00010010110001111 +`define VFSSEGW 32'b???????????????00010010100001111 +`define VSSEGSTD 32'b????????????????????100110001111 +`define VSSEGSTW 32'b????????????????????100100001111 +`define VSSEGSTH 32'b????????????????????100010001111 +`define VSSEGSTB 32'b????????????????????100000001111 +`define VFSSEGSTD 32'b????????????????????110110001111 +`define VFSSEGSTW 32'b????????????????????110100001111 +`define VMVV 32'b??????????0000000000000001110011 +`define VMSV 32'b??????????0000000000100001110011 +`define VMST 32'b???????????????00001000001110011 +`define VMTS 32'b???????????????00001100001110011 +`define VFMVV 32'b??????????0000000000000101110011 +`define VFMSV 32'b??????????0000000000100101110011 +`define VFMST 32'b???????????????00001000101110011 +`define VFMTS 32'b???????????????00001100101110011 +`define VVCFG 32'b00000??????????00000010001110011 +`define VTCFG 32'b00000??????????00000110001110011 +`define VVCFGIVL 32'b??????????????????????0011110011 +`define VTCFGIVL 32'b??????????????????????0111110011 +`define VSETVL 32'b??????????0000000000001011110011 +`define VF 32'b00000?????????????????1111110011 +`define C_LI 32'b???????????????????????????00000 +`define C_ADDI 32'b???????????????????????????00001 +`define C_ADDIW 32'b???????????????????????????11101 +`define C_LDSP 32'b???????????????????????????00100 +`define C_LWSP 32'b???????????????????????????00101 +`define C_SDSP 32'b???????????????????????????00110 +`define C_SWSP 32'b???????????????????????????01000 +`define C_LW0 32'b????????????????0??????????10010 +`define C_LD0 32'b????????????????1??????????10010 +`define C_ADD 32'b????????????????0??????????11010 +`define C_SUB 32'b????????????????1??????????11010 +`define C_MOVE 32'b????????????????0??????????00010 +`define C_J 32'b????????????????1??????????00010 +`define C_LD 32'b???????????????????????????01001 +`define C_LW 32'b???????????????????????????01010 +`define C_SD 32'b???????????????????????????01100 +`define C_SW 32'b???????????????????????????01101 +`define C_BEQ 32'b???????????????????????????10000 +`define C_BNE 32'b???????????????????????????10001 +`define C_FLW 32'b???????????????????????????10100 +`define C_FLD 32'b???????????????????????????10101 +`define C_FSW 32'b???????????????????????????10110 +`define C_FSD 32'b???????????????????????????11000 +`define C_SLLI 32'b???????????????????000?????11001 +`define C_SLLI32 32'b???????????????????001?????11001 +`define C_SRLI 32'b???????????????????010?????11001 +`define C_SRLI32 32'b???????????????????011?????11001 +`define C_SRAI 32'b???????????????????100?????11001 +`define C_SRAI32 32'b???????????????????101?????11001 +`define C_SLLIW 32'b???????????????????110?????11001 +`define C_ADD3 32'b??????????????????????00???11100 +`define C_SUB3 32'b??????????????????????01???11100 +`define C_OR3 32'b??????????????????????10???11100 +`define C_AND3 32'b??????????????????????11???11100 diff --git a/instr-table.tex b/instr-table.tex index c1761be..b6375da 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -5,17 +5,6 @@ \begin{small} \begin{center} \begin{tabular}{rccccccccccl} - & -\hspace*{0.6in} & -\hspace*{0.3in} & -\hspace*{0.1in} & -\hspace*{0.1in} & -\hspace*{0.2in} & -\hspace*{0.2in} & -\hspace*{0.1in} & -\hspace*{0.3in} & -\hspace*{0.3in} & -\hspace*{0.3in} \\ & \instbitrange{31}{27} & \instbitrange{26}{22} & @@ -34,8 +23,8 @@ \cline{2-11} & \multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & -\multicolumn{1}{c|}{opcode} & LUI-type \\ +\multicolumn{8}{c|}{upper immediate} & +\multicolumn{1}{c|}{opcode} & U-type \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & @@ -73,19 +62,21 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf Unimplemented Instruction} & \\ +\multicolumn{10}{c}{\bf RV32I Instruction Subset} & \\ \cline{2-11} & -\multicolumn{10}{|c|}{00000000000000000000000000000000} & UNIMP \\ +\multicolumn{1}{|c|}{rd} & +\multicolumn{8}{c|}{imm20} & +\multicolumn{1}{c|}{0110111} & LUI rd,imm20 \\ \cline{2-11} & -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf Control Transfer Instructions} & \\ +\multicolumn{1}{|c|}{rd} & +\multicolumn{8}{c|}{imm20} & +\multicolumn{1}{c|}{0010111} & AUIPC rd,imm20 \\ \cline{2-11} @@ -102,6 +93,15 @@ & +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1101011} & JALR rd,rs1,imm12 \\ +\cline{2-11} + + +& \multicolumn{1}{|c|}{imm12hi} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & @@ -166,40 +166,6 @@ \multicolumn{1}{c|}{rs1} & \multicolumn{5}{c|}{imm12} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{1101011} & JALR.C rd,rs1,imm12 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{1101011} & JALR.R rd,rs1,imm12 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{1101011} & JALR.J rd,rs1,imm12 \\ -\cline{2-11} - - -& -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf Memory Instructions} & \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{000} & \multicolumn{1}{c|}{0000011} & LB rd,rs1,imm12 \\ \cline{2-11} @@ -226,15 +192,6 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0000011} & LD rd,rs1,imm12 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & \multicolumn{2}{c|}{100} & \multicolumn{1}{c|}{0000011} & LBU rd,rs1,imm12 \\ \cline{2-11} @@ -250,15 +207,6 @@ & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{110} & -\multicolumn{1}{c|}{0000011} & LWU rd,rs1,imm12 \\ -\cline{2-11} - - -& \multicolumn{1}{|c|}{imm12hi} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & @@ -289,79 +237,86 @@ & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0100011} & SD rs1,rs2,imm12 \\ +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{0010011} & ADDI rd,rs1,imm12 \\ \cline{2-11} & -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf Atomic Memory Instructions} & \\ +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{2}{c|}{000000} & +\multicolumn{3}{c|}{shamt} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{0010011} & SLLI rd,rs1,shamt \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & +\multicolumn{5}{c|}{imm12} & \multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOADD.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{0010011} & SLTI rd,rs1,imm12 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOSWAP.W rd,rs1,rs2 \\ +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0010011} & SLTIU rd,rs1,imm12 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000010} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOAND.W rd,rs1,rs2 \\ +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{0010011} & XORI rd,rs1,imm12 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000011} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOOR.W rd,rs1,rs2 \\ +\multicolumn{2}{c|}{000000} & +\multicolumn{3}{c|}{shamt} & +\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{0010011} & SRLI rd,rs1,shamt \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000100} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMIN.W rd,rs1,rs2 \\ +\multicolumn{2}{c|}{000001} & +\multicolumn{3}{c|}{shamt} & +\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{0010011} & SRAI rd,rs1,shamt \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000101} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMAX.W rd,rs1,rs2 \\ +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{0010011} & ORI rd,rs1,imm12 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{111} & +\multicolumn{1}{c|}{0010011} & ANDI rd,rs1,imm12 \\ \cline{2-11} @@ -369,9 +324,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000110} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMINU.W rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{0110011} & ADD rd,rs1,rs2 \\ \cline{2-11} @@ -379,9 +334,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000111} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & AMOMAXU.W rd,rs1,rs2 \\ +\multicolumn{4}{c|}{1000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{0110011} & SUB rd,rs1,rs2 \\ \cline{2-11} @@ -390,8 +345,8 @@ \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & \multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOADD.D rd,rs1,rs2 \\ +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{0110011} & SLL rd,rs1,rs2 \\ \cline{2-11} @@ -399,9 +354,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOSWAP.D rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0110011} & SLT rd,rs1,rs2 \\ \cline{2-11} @@ -409,9 +364,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000010} & +\multicolumn{4}{c|}{0000000} & \multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOAND.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{0110011} & SLTU rd,rs1,rs2 \\ \cline{2-11} @@ -419,9 +374,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000011} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOOR.D rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{0110011} & XOR rd,rs1,rs2 \\ \cline{2-11} @@ -429,9 +384,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000100} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMIN.D rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{0110011} & SRL rd,rs1,rs2 \\ \cline{2-11} @@ -439,9 +394,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000101} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMAX.D rd,rs1,rs2 \\ +\multicolumn{4}{c|}{1000000} & +\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{0110011} & SRA rd,rs1,rs2 \\ \cline{2-11} @@ -449,9 +404,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000110} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMINU.D rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{0110011} & OR rd,rs1,rs2 \\ \cline{2-11} @@ -459,49 +414,77 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000111} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & AMOMAXU.D rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{111} & +\multicolumn{1}{c|}{0110011} & AND rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & LR.W rd,rs1 \\ +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{0101111} & FENCE.I rd,rs1,imm12 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101111} & FENCE rd,rs1,imm12 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{00000} & \multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & LR.D rd,rs1 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1110111} & SYSCALL \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{1110111} & BREAK \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000001} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101011} & SC.W rd,rs1,rs2 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{1110111} & RDCYCLE rd \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000001} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0101011} & SC.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000001} & +\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{1110111} & RDTIME rd \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{0000010} & +\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{1110111} & RDINSTRET rd \\ \cline{2-11} @@ -519,17 +502,6 @@ \begin{small} \begin{center} \begin{tabular}{rccccccccccl} - & -\hspace*{0.6in} & -\hspace*{0.3in} & -\hspace*{0.1in} & -\hspace*{0.1in} & -\hspace*{0.2in} & -\hspace*{0.2in} & -\hspace*{0.1in} & -\hspace*{0.3in} & -\hspace*{0.3in} & -\hspace*{0.3in} \\ & \instbitrange{31}{27} & \instbitrange{26}{22} & @@ -548,8 +520,8 @@ \cline{2-11} & \multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & -\multicolumn{1}{c|}{opcode} & LUI-type \\ +\multicolumn{8}{c|}{upper immediate} & +\multicolumn{1}{c|}{opcode} & U-type \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & @@ -587,7 +559,7 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf Integer Compute Instructions} & \\ +\multicolumn{10}{c}{\bf RV64I Instruction Subset} & \\ \cline{2-11} @@ -595,18 +567,8 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0010011} & ADDI rd,rs1,imm12 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000000} & -\multicolumn{3}{c|}{shamt} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0010011} & SLLI rd,rs1,shamt \\ +\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{0000011} & LWU rd,rs1,imm12 \\ \cline{2-11} @@ -614,17 +576,18 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0010011} & SLTI rd,rs1,imm12 \\ +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0000011} & LD rd,rs1,imm12 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{|c|}{imm12hi} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{imm12lo} & \multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0010011} & SLTIU rd,rs1,imm12 \\ +\multicolumn{1}{c|}{0100011} & SD rs1,rs2,imm12 \\ \cline{2-11} @@ -632,46 +595,38 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{0010011} & XORI rd,rs1,imm12 \\ +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{0011011} & ADDIW rd,rs1,imm12 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000000} & -\multicolumn{3}{c|}{shamt} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0010011} & SRLI rd,rs1,shamt \\ +\multicolumn{3}{c|}{0000000} & +\multicolumn{2}{c|}{shamtw} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{0011011} & SLLIW rd,rs1,shamtw \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{000001} & -\multicolumn{3}{c|}{shamt} & +\multicolumn{3}{c|}{0000000} & +\multicolumn{2}{c|}{shamtw} & \multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0010011} & SRAI rd,rs1,shamt \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{110} & -\multicolumn{1}{c|}{0010011} & ORI rd,rs1,imm12 \\ +\multicolumn{1}{c|}{0011011} & SRLIW rd,rs1,shamtw \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{111} & -\multicolumn{1}{c|}{0010011} & ANDI rd,rs1,imm12 \\ +\multicolumn{3}{c|}{0000010} & +\multicolumn{2}{c|}{shamtw} & +\multicolumn{2}{c|}{101} & +\multicolumn{1}{c|}{0011011} & SRAIW rd,rs1,shamtw \\ \cline{2-11} @@ -681,7 +636,7 @@ \multicolumn{1}{c|}{rs2} & \multicolumn{4}{c|}{0000000} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0110011} & ADD rd,rs1,rs2 \\ +\multicolumn{1}{c|}{0111011} & ADDW rd,rs1,rs2 \\ \cline{2-11} @@ -691,7 +646,7 @@ \multicolumn{1}{c|}{rs2} & \multicolumn{4}{c|}{1000000} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0110011} & SUB rd,rs1,rs2 \\ +\multicolumn{1}{c|}{0111011} & SUBW rd,rs1,rs2 \\ \cline{2-11} @@ -701,37 +656,7 @@ \multicolumn{1}{c|}{rs2} & \multicolumn{4}{c|}{0000000} & \multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0110011} & SLL rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0110011} & SLT rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0110011} & SLTU rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{0110011} & XOR rd,rs1,rs2 \\ +\multicolumn{1}{c|}{0111011} & SLLW rd,rs1,rs2 \\ \cline{2-11} @@ -741,7 +666,7 @@ \multicolumn{1}{c|}{rs2} & \multicolumn{4}{c|}{0000000} & \multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0110011} & SRL rd,rs1,rs2 \\ +\multicolumn{1}{c|}{0111011} & SRLW rd,rs1,rs2 \\ \cline{2-11} @@ -751,27 +676,14 @@ \multicolumn{1}{c|}{rs2} & \multicolumn{4}{c|}{1000000} & \multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0110011} & SRA rd,rs1,rs2 \\ +\multicolumn{1}{c|}{0111011} & SRAW rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{110} & -\multicolumn{1}{c|}{0110011} & OR rd,rs1,rs2 \\ -\cline{2-11} - - +\multicolumn{10}{c}{} & \\ & -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{111} & -\multicolumn{1}{c|}{0110011} & AND rd,rs1,rs2 \\ +\multicolumn{10}{c}{\bf RV32M Instruction Subset} & \\ \cline{2-11} @@ -856,55 +768,49 @@ & -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{imm20} & -\multicolumn{1}{c|}{0110111} & LUI rd,imm20 \\ -\cline{2-11} - - -& \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf 32-bit Integer Compute Instructions} & \\ +\multicolumn{10}{c}{\bf RV64M Instruction Subset} & \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000001} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0011011} & ADDIW rd,rs1,imm12 \\ +\multicolumn{1}{c|}{0111011} & MULW rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{3}{c|}{0000000} & -\multicolumn{2}{c|}{shamtw} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0011011} & SLLIW rd,rs1,shamtw \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000001} & +\multicolumn{2}{c|}{100} & +\multicolumn{1}{c|}{0111011} & DIVW rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{3}{c|}{0000000} & -\multicolumn{2}{c|}{shamtw} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000001} & \multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0011011} & SRLIW rd,rs1,shamtw \\ +\multicolumn{1}{c|}{0111011} & DIVUW rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{3}{c|}{0000010} & -\multicolumn{2}{c|}{shamtw} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0011011} & SRAIW rd,rs1,shamtw \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000001} & +\multicolumn{2}{c|}{110} & +\multicolumn{1}{c|}{0111011} & REMW rd,rs1,rs2 \\ \cline{2-11} @@ -912,9 +818,16 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0111011} & ADDW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000001} & +\multicolumn{2}{c|}{111} & +\multicolumn{1}{c|}{0111011} & REMUW rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{10}{c}{} & \\ +& +\multicolumn{10}{c}{\bf RV32A Instruction Subset} & \\ \cline{2-11} @@ -922,9 +835,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0111011} & SUBW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOADD.W rd,rs1,rs2 \\ \cline{2-11} @@ -932,9 +845,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0111011} & SLLW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000001} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOSWAP.W rd,rs1,rs2 \\ \cline{2-11} @@ -942,9 +855,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0111011} & SRLW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000010} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOAND.W rd,rs1,rs2 \\ \cline{2-11} @@ -952,9 +865,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{1000000} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0111011} & SRAW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000011} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOOR.W rd,rs1,rs2 \\ \cline{2-11} @@ -962,9 +875,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{0111011} & MULW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000100} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOMIN.W rd,rs1,rs2 \\ \cline{2-11} @@ -972,9 +885,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{0111011} & DIVW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000101} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOMAX.W rd,rs1,rs2 \\ \cline{2-11} @@ -982,9 +895,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0111011} & DIVUW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000110} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOMINU.W rd,rs1,rs2 \\ \cline{2-11} @@ -992,9 +905,19 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{110} & -\multicolumn{1}{c|}{0111011} & REMW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{0000111} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & AMOMAXU.W rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1000000} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & LR.W rd,rs1 \\ \cline{2-11} @@ -1002,9 +925,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{111} & -\multicolumn{1}{c|}{0111011} & REMUW rd,rs1,rs2 \\ +\multicolumn{4}{c|}{1000001} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0101011} & SC.W rd,rs1,rs2 \\ \cline{2-11} @@ -1022,17 +945,6 @@ \begin{small} \begin{center} \begin{tabular}{rccccccccccl} - & -\hspace*{0.6in} & -\hspace*{0.3in} & -\hspace*{0.1in} & -\hspace*{0.1in} & -\hspace*{0.2in} & -\hspace*{0.2in} & -\hspace*{0.1in} & -\hspace*{0.3in} & -\hspace*{0.3in} & -\hspace*{0.3in} \\ & \instbitrange{31}{27} & \instbitrange{26}{22} & @@ -1051,8 +963,8 @@ \cline{2-11} & \multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & -\multicolumn{1}{c|}{opcode} & LUI-type \\ +\multicolumn{8}{c|}{upper immediate} & +\multicolumn{1}{c|}{opcode} & U-type \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & @@ -1090,52 +1002,133 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf Floating-Point Memory Instructions} & \\ +\multicolumn{10}{c}{\bf RV64A Instruction Subset} & \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0000111} & FLW rd,rs1,imm12 \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000000} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & AMOADD.D rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000001} & \multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0000111} & FLD rd,rs1,imm12 \\ +\multicolumn{1}{c|}{0101011} & AMOSWAP.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0100111} & FSW rs1,rs2,imm12 \\ +\multicolumn{4}{c|}{0000010} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & AMOAND.D rd,rs1,rs2 \\ \cline{2-11} & -\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm12lo} & +\multicolumn{4}{c|}{0000011} & \multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{0100111} & FSD rs1,rs2,imm12 \\ +\multicolumn{1}{c|}{0101011} & AMOOR.D rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000100} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & AMOMIN.D rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000101} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & AMOMAX.D rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000110} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & AMOMINU.D rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0000111} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & AMOMAXU.D rd,rs1,rs2 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1000000} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & LR.D rd,rs1 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{1000001} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0101011} & SC.D rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf Floating-Point Compute Instructions} & \\ +\multicolumn{10}{c}{\bf RV32F Instruction Subset} & \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0000111} & FLW rd,rs1,imm12 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{imm12hi} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{imm12lo} & +\multicolumn{2}{c|}{010} & +\multicolumn{1}{c|}{0100111} & FSW rs1,rs2,imm12 \\ \cline{2-11} @@ -1146,7 +1139,7 @@ \multicolumn{3}{c|}{00000} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FADD.S rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{1010011} & FADD.S rd,rs1,rs2,rm \\ \cline{2-11} @@ -1157,7 +1150,7 @@ \multicolumn{3}{c|}{00001} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FSUB.S rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{1010011} & FSUB.S rd,rs1,rs2,rm \\ \cline{2-11} @@ -1168,7 +1161,7 @@ \multicolumn{3}{c|}{00010} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FMUL.S rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{1010011} & FMUL.S rd,rs1,rs2,rm \\ \cline{2-11} @@ -1179,7 +1172,7 @@ \multicolumn{3}{c|}{00011} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FDIV.S rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{1010011} & FDIV.S rd,rs1,rs2,rm \\ \cline{2-11} @@ -1190,7 +1183,7 @@ \multicolumn{3}{c|}{00100} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FSQRT.S rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FSQRT.S rd,rs1,rm \\ \cline{2-11} @@ -1198,9 +1191,8 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11000} & +\multicolumn{4}{c|}{1100000} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & \multicolumn{1}{c|}{1010011} & FMIN.S rd,rs1,rs2 \\ \cline{2-11} @@ -1209,9 +1201,8 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11001} & +\multicolumn{4}{c|}{1100100} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & \multicolumn{1}{c|}{1010011} & FMAX.S rd,rs1,rs2 \\ \cline{2-11} @@ -1220,10 +1211,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00000} & +\multicolumn{3}{c|}{rs3} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FADD.D rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{1000011} & FMADD.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} @@ -1231,10 +1222,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00001} & +\multicolumn{3}{c|}{rs3} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FSUB.D rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{1000111} & FMSUB.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} @@ -1242,10 +1233,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00010} & +\multicolumn{3}{c|}{rs3} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FMUL.D rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{1001011} & FNMSUB.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} @@ -1253,21 +1244,20 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00011} & +\multicolumn{3}{c|}{rs3} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FDIV.D rd,rs1,rs2[,rm] \\ +\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{1001111} & FNMADD.S rd,rs1,rs2,rs3,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{00100} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FSQRT.D rd,rs1[,rm] \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0010100} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & FSGNJ.S rd,rs1,rs2 \\ \cline{2-11} @@ -1275,10 +1265,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11000} & +\multicolumn{4}{c|}{0011000} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FMIN.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{1010011} & FSGNJN.S rd,rs1,rs2 \\ \cline{2-11} @@ -1286,65 +1275,93 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{11001} & +\multicolumn{4}{c|}{0011100} & \multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FMAX.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{1010011} & FSGNJX.S rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01110} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1000011} & FMADD.S rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.S.W rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01111} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1000111} & FMSUB.S rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.S.WU rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1111000} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & MXTF.S rd,rs1 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1111100} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & MTFSR rd,rs1 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01010} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1001011} & FNMSUB.S rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.W.S rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01011} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1001111} & FNMADD.S rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.WU.S rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1000011} & FMADD.D rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1110000} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & MFTX.S rd,rs1 \\ +\cline{2-11} + + +& +\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{00000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1110100} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & MFFSR rd \\ \cline{2-11} @@ -1352,10 +1369,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1000111} & FMSUB.D rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{4}{c|}{1010100} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & FEQ.S rd,rs1,rs2 \\ \cline{2-11} @@ -1363,10 +1379,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1001011} & FNMSUB.D rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{4}{c|}{1011000} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & FLT.S rd,rs1,rs2 \\ \cline{2-11} @@ -1374,10 +1389,9 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1001111} & FNMADD.D rd,rs1,rs2,rs3[,rm] \\ +\multicolumn{4}{c|}{1011100} & +\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{1010011} & FLE.S rd,rs1,rs2 \\ \cline{2-11} @@ -1395,17 +1409,6 @@ \begin{small} \begin{center} \begin{tabular}{rccccccccccl} - & -\hspace*{0.6in} & -\hspace*{0.3in} & -\hspace*{0.1in} & -\hspace*{0.1in} & -\hspace*{0.2in} & -\hspace*{0.2in} & -\hspace*{0.1in} & -\hspace*{0.3in} & -\hspace*{0.3in} & -\hspace*{0.3in} \\ & \instbitrange{31}{27} & \instbitrange{26}{22} & @@ -1424,8 +1427,8 @@ \cline{2-11} & \multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & -\multicolumn{1}{c|}{opcode} & LUI-type \\ +\multicolumn{8}{c|}{upper immediate} & +\multicolumn{1}{c|}{opcode} & U-type \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & @@ -1463,73 +1466,29 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf Floating-Point Move \& Conversion Instructions} & \\ +\multicolumn{10}{c}{\bf RV64F Instruction Subset} & \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FSGNJ.S rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00110} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01100} & +\multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FSGNJN.S rd,rs1,rs2 \\ +\multicolumn{1}{c|}{1010011} & FCVT.S.L rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00111} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01101} & +\multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FSGNJX.S rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FSGNJ.D rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FSGNJN.D rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{00111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FSGNJX.D rd,rs1,rs2 \\ +\multicolumn{1}{c|}{1010011} & FCVT.S.LU rd,rs1,rm \\ \cline{2-11} @@ -1537,10 +1496,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{10001} & +\multicolumn{3}{c|}{01000} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.S.D rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.L.S rd,rs1,rm \\ \cline{2-11} @@ -1548,83 +1507,80 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{10000} & +\multicolumn{3}{c|}{01001} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.D.S rd,rs1[,rm] \\ +\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{1010011} & FCVT.LU.S rd,rs1,rm \\ \cline{2-11} & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf Integer to Floating-Point Move \& Conversion Instructions} & \\ +\multicolumn{10}{c}{\bf RV32D Instruction Subset} & \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01100} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.S.L rd,rs1[,rm] \\ +\multicolumn{5}{c|}{imm12} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0000111} & FLD rd,rs1,imm12 \\ \cline{2-11} & -\multicolumn{1}{|c|}{rd} & +\multicolumn{1}{|c|}{imm12hi} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01101} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.S.LU rd,rs1[,rm] \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{imm12lo} & +\multicolumn{2}{c|}{011} & +\multicolumn{1}{c|}{0100111} & FSD rs1,rs2,imm12 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01110} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{00000} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.S.W rd,rs1[,rm] \\ +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1010011} & FADD.D rd,rs1,rs2,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01111} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{00001} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.S.WU rd,rs1[,rm] \\ +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1010011} & FSUB.D rd,rs1,rs2,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01100} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{00010} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.D.L rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FMUL.D rd,rs1,rs2,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01101} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{00011} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.D.LU rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FDIV.D rd,rs1,rs2,rm \\ \cline{2-11} @@ -1632,116 +1588,104 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01110} & +\multicolumn{3}{c|}{00100} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.D.W rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FSQRT.D rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01111} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.D.WU rd,rs1[,rm] \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{1100000} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{1010011} & FMIN.D rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & MXTF.S rd,rs1 \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{1100100} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{1010011} & FMAX.D rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11110} & -\multicolumn{2}{c|}{000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{rs3} & +\multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & MXTF.D rd,rs1 \\ +\multicolumn{1}{c|}{1000011} & FMADD.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & MTFSR rd,rs1 \\ -\cline{2-11} - - -& -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf Floating-Point to Integer Move \& Conversion Instructions} & \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{rs3} & +\multicolumn{2}{c|}{rm} & +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1000111} & FMSUB.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01000} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{rs3} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.L.S rd,rs1[,rm] \\ +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1001011} & FNMSUB.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01001} & +\multicolumn{1}{c|}{rs2} & +\multicolumn{3}{c|}{rs3} & \multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.LU.S rd,rs1[,rm] \\ +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1001111} & FNMADD.D rd,rs1,rs2,rs3,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01010} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.W.S rd,rs1[,rm] \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0010100} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{1010011} & FSGNJ.D rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01011} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FCVT.WU.S rd,rs1[,rm] \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0011000} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{1010011} & FSGNJN.D rd,rs1,rs2 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01000} & -\multicolumn{2}{c|}{rm} & -\multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.L.D rd,rs1[,rm] \\ +\multicolumn{1}{c|}{rs2} & +\multicolumn{4}{c|}{0011100} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{1010011} & FSGNJX.D rd,rs1,rs2 \\ \cline{2-11} @@ -1749,10 +1693,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01001} & +\multicolumn{3}{c|}{01110} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.LU.D rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.D.W rd,rs1,rm \\ \cline{2-11} @@ -1760,10 +1704,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01010} & +\multicolumn{3}{c|}{01111} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.W.D rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.D.WU rd,rs1,rm \\ \cline{2-11} @@ -1771,10 +1715,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{01011} & +\multicolumn{3}{c|}{01010} & \multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & FCVT.WU.D rd,rs1[,rm] \\ +\multicolumn{1}{c|}{1010011} & FCVT.W.D rd,rs1,rm \\ \cline{2-11} @@ -1782,129 +1726,10 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11100} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & MFTX.S rd,rs1 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11100} & -\multicolumn{2}{c|}{000} & +\multicolumn{3}{c|}{01011} & +\multicolumn{2}{c|}{rm} & \multicolumn{1}{c|}{01} & -\multicolumn{1}{c|}{1010011} & MFTX.D rd,rs1 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{3}{c|}{11101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & MFFSR rd \\ -\cline{2-11} - - -\end{tabular} -\end{center} -\end{small} - -\label{instr-table} -\end{table} - - -\newpage - -\begin{table}[p] -\begin{small} -\begin{center} -\begin{tabular}{rccccccccccl} - & -\hspace*{0.6in} & -\hspace*{0.3in} & -\hspace*{0.1in} & -\hspace*{0.1in} & -\hspace*{0.2in} & -\hspace*{0.2in} & -\hspace*{0.1in} & -\hspace*{0.3in} & -\hspace*{0.3in} & -\hspace*{0.3in} \\ - & -\instbitrange{31}{27} & -\instbitrange{26}{22} & -\instbitrange{21}{17} & -\instbit{16} & -\instbit{15} & -\instbitrange{14}{12} & -\instbitrange{11}{10} & -\instbit{9} & -\instbitrange{8}{7} & -\instbitrange{6}{0} \\ -\cline{2-11} -& -\multicolumn{9}{|c|}{jump target} & -\multicolumn{1}{c|}{opcode} & J-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{8}{c|}{LUI-immediate} & -\multicolumn{1}{c|}{opcode} & LUI-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{imm[11:7]} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & I-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{imm[11:7]} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{imm[6:0]} & -\multicolumn{2}{c|}{funct3} & -\multicolumn{1}{c|}{opcode} & B-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{6}{c|}{funct10} & -\multicolumn{1}{c|}{opcode} & R-type \\ -\cline{2-11} -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{rs3} & -\multicolumn{3}{c|}{funct5} & -\multicolumn{1}{c|}{opcode} & R4-type \\ -\cline{2-11} - - -& -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf Floating-Point Compare Instructions} & \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FEQ.S rd,rs1,rs2 \\ +\multicolumn{1}{c|}{1010011} & FCVT.WU.D rd,rs1,rm \\ \cline{2-11} @@ -1912,31 +1737,8 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FLT.S rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{00} & -\multicolumn{1}{c|}{1010011} & FLE.S rd,rs1,rs2 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10101} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{4}{c|}{1010100} & +\multicolumn{2}{c|}{001} & \multicolumn{1}{c|}{1010011} & FEQ.D rd,rs1,rs2 \\ \cline{2-11} @@ -1945,9 +1747,8 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10110} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{4}{c|}{1011000} & +\multicolumn{2}{c|}{001} & \multicolumn{1}{c|}{1010011} & FLT.D rd,rs1,rs2 \\ \cline{2-11} @@ -1956,9 +1757,8 @@ \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{rs2} & -\multicolumn{3}{c|}{10111} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{01} & +\multicolumn{4}{c|}{1011100} & +\multicolumn{2}{c|}{001} & \multicolumn{1}{c|}{1010011} & FLE.D rd,rs1,rs2 \\ \cline{2-11} @@ -1966,160 +1766,93 @@ & \multicolumn{10}{c}{} & \\ & -\multicolumn{10}{c}{\bf Miscellaneous Memory Instructions} & \\ +\multicolumn{10}{c}{\bf RV64D Instruction Subset} & \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{0101111} & FENCE.I rd,rs1,imm12 \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{0101111} & FENCE rd,rs1,imm12 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01100} & +\multicolumn{2}{c|}{rm} & +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1010011} & FCVT.D.L rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{0101111} & FENCE.V.L rd,rs1,imm12 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01101} & +\multicolumn{2}{c|}{rm} & +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1010011} & FCVT.D.LU rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{5}{c|}{imm12} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{0101111} & FENCE.V.G rd,rs1,imm12 \\ -\cline{2-11} - - -& -\multicolumn{10}{c}{} & \\ -& -\multicolumn{10}{c}{\bf System Instructions} & \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{000} & -\multicolumn{1}{c|}{1110111} & SYSCALL \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{00000} & -\multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & +\multicolumn{4}{c|}{1111000} & \multicolumn{2}{c|}{001} & -\multicolumn{1}{c|}{1110111} & BREAK \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{1110111} & RDCYCLE rd \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{1110111} & RDTIME rd \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{rd} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000010} & -\multicolumn{2}{c|}{100} & -\multicolumn{1}{c|}{1110111} & RDINSTRET rd \\ -\cline{2-11} - - -& -\multicolumn{1}{|c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{010} & -\multicolumn{1}{c|}{1110111} & STOP \\ +\multicolumn{1}{c|}{1010011} & MXTF.D rd,rs1 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & +\multicolumn{1}{c|}{rs1} & \multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{00000} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{011} & -\multicolumn{1}{c|}{1110111} & UTIDX rd \\ +\multicolumn{3}{c|}{01000} & +\multicolumn{2}{c|}{rm} & +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1010011} & FCVT.L.D rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000000} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{1110111} & MOVZ rd,rs1,rs2 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{01001} & +\multicolumn{2}{c|}{rm} & +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1010011} & FCVT.LU.D rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000001} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{1110111} & MOVN rd,rs1,rs2 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{4}{c|}{1110000} & +\multicolumn{2}{c|}{001} & +\multicolumn{1}{c|}{1010011} & MFTX.D rd,rs1 \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000010} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{1110111} & FMOVZ rd,rs1,rs2 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{10001} & +\multicolumn{2}{c|}{rm} & +\multicolumn{1}{c|}{00} & +\multicolumn{1}{c|}{1010011} & FCVT.S.D rd,rs1,rm \\ \cline{2-11} & \multicolumn{1}{|c|}{rd} & \multicolumn{1}{c|}{rs1} & -\multicolumn{1}{c|}{rs2} & -\multicolumn{4}{c|}{0000011} & -\multicolumn{2}{c|}{101} & -\multicolumn{1}{c|}{1110111} & FMOVN rd,rs1,rs2 \\ +\multicolumn{1}{c|}{00000} & +\multicolumn{3}{c|}{10000} & +\multicolumn{2}{c|}{rm} & +\multicolumn{1}{c|}{01} & +\multicolumn{1}{c|}{1010011} & FCVT.D.S rd,rs1,rm \\ \cline{2-11} @@ -1,10 +1,11 @@ # format of a line in this file: -# <instruction name> <opcode> <args> +# <instruction name> <args> <opcode> # # <opcode> is given by specifying one or more range/value pairs: -# highbit..lowbit=value (e.g. 6..2=0x45 9..7=0x0) +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) # -# <args> is one of xa,xb,xc,fa,fb,fc,fd,imm,imm20,imm27,shamt,shamtw +# <args> is one of rd, rs1, rs2, rs3, imm25, imm20, imm12, imm12lo, imm12hi, +# shamtw, shamt, rm j imm25 6..2=0x19 1..0=3 jal imm25 6..2=0x1B 1..0=3 @@ -76,9 +77,9 @@ lbu rd rs1 imm12 9..7=4 6..2=0x00 1..0=3 lhu rd rs1 imm12 9..7=5 6..2=0x00 1..0=3 lwu rd rs1 imm12 9..7=6 6..2=0x00 1..0=3 -# NOTE: if you add new store instructions, make sure to modify tc-mips-riscv.c -# and elfxx-mips.c to detect them. this is a hack to handle the split immed. -# just open up those files and search for MATCH_SW; should be obvious. +# XXX If you add new store instructions, make sure to modify tc-riscv.c and +# elfxx-riscv.c to detect them; the split immediate is handled therein. +# search for MATCH_SW and continue this inglorious hack in the obvious way. sb imm12hi rs1 rs2 imm12lo 9..7=0 6..2=0x08 1..0=3 sh imm12hi rs1 rs2 imm12lo 9..7=1 6..2=0x08 1..0=3 sw imm12hi rs1 rs2 imm12lo 9..7=2 6..2=0x08 1..0=3 @@ -118,31 +119,13 @@ rdcycle rd 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1D 1..0=3 rdtime rd 26..22=0 21..17=0 16..10=1 9..7=4 6..2=0x1D 1..0=3 rdinstret rd 26..22=0 21..17=0 16..10=2 9..7=4 6..2=0x1D 1..0=3 -# vector scalar instructions -stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3 -utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3 -movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3 -movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3 -fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3 -fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3 - +# SUPERVISOR clearpcr rd rs1 imm12 9..7=0 6..2=0x1E 1..0=3 setpcr rd rs1 imm12 9..7=1 6..2=0x1E 1..0=3 mfpcr rd rs1 21..17=0 16..10=0 9..7=2 6..2=0x1E 1..0=3 mtpcr rd rs1 rs2 16..10=0 9..7=3 6..2=0x1E 1..0=3 eret 31..27=0 26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1E 1..0=3 -vxcptsave 31..27=0 rs1 21..17=0 16..10=0x0 9..7=6 6..2=0x1E 1..0=3 -vxcptrestore 31..27=0 rs1 21..17=0 16..10=0x1 9..7=6 6..2=0x1E 1..0=3 -vxcptkill 31..27=0 26..22=0 21..17=0 16..10=0x2 9..7=6 6..2=0x1E 1..0=3 - -vxcptevac 31..27=0 rs1 21..17=0 16..10=0x8 9..7=6 6..2=0x1E 1..0=3 -vxcpthold 31..27=0 26..22=0 21..17=0 16..10=0x9 9..7=6 6..2=0x1E 1..0=3 -venqcmd 31..27=0 rs1 rs2 16..10=0xA 9..7=6 6..2=0x1E 1..0=3 -venqimm1 31..27=0 rs1 rs2 16..10=0xB 9..7=6 6..2=0x1E 1..0=3 -venqimm2 31..27=0 rs1 rs2 16..10=0xC 9..7=6 6..2=0x1E 1..0=3 -venqcnt 31..27=0 rs1 rs2 16..10=0xD 9..7=6 6..2=0x1E 1..0=3 - # 0x7C-0x7F are reserved for >32b instructions fadd.s rd rs1 rs2 16..12=0 rm 8..7=0 6..2=0x14 1..0=3 @@ -223,6 +206,25 @@ fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 +# vector scalar instructions +stop 31..27=0 26..22=0 21..17=0 16..10=0 9..7=2 6..2=0x1D 1..0=3 +utidx rd 26..22=0 21..17=0 16..10=0 9..7=3 6..2=0x1D 1..0=3 +movz rd rs1 rs2 16..10=0 9..7=5 6..2=0x1D 1..0=3 +movn rd rs1 rs2 16..10=1 9..7=5 6..2=0x1D 1..0=3 +fmovz rd rs1 rs2 16..10=2 9..7=5 6..2=0x1D 1..0=3 +fmovn rd rs1 rs2 16..10=3 9..7=5 6..2=0x1D 1..0=3 + +vxcptsave 31..27=0 rs1 21..17=0 16..10=0x0 9..7=6 6..2=0x1E 1..0=3 +vxcptrestore 31..27=0 rs1 21..17=0 16..10=0x1 9..7=6 6..2=0x1E 1..0=3 +vxcptkill 31..27=0 26..22=0 21..17=0 16..10=0x2 9..7=6 6..2=0x1E 1..0=3 + +vxcptevac 31..27=0 rs1 21..17=0 16..10=0x8 9..7=6 6..2=0x1E 1..0=3 +vxcpthold 31..27=0 26..22=0 21..17=0 16..10=0x9 9..7=6 6..2=0x1E 1..0=3 +venqcmd 31..27=0 rs1 rs2 16..10=0xA 9..7=6 6..2=0x1E 1..0=3 +venqimm1 31..27=0 rs1 rs2 16..10=0xB 9..7=6 6..2=0x1E 1..0=3 +venqimm2 31..27=0 rs1 rs2 16..10=0xC 9..7=6 6..2=0x1E 1..0=3 +venqcnt 31..27=0 rs1 rs2 16..10=0xD 9..7=6 6..2=0x1E 1..0=3 + # vector load mem instructions # 3=d diff --git a/parse-opcodes b/parse-opcodes index 260634b..19a8bb9 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -8,7 +8,6 @@ namelist = [] match = {} mask = {} arguments = {} -types = {} arglut = {} arglut['rd'] = (31,27) @@ -114,7 +113,6 @@ def str_inst(name,arguments): ret = ret + arguments[idx] if idx != len(arguments)-1: ret = ret + ',' - ret = ret.replace(',rm','[,rm]') return ret def print_unimp_type(name,match,arguments): @@ -334,17 +332,6 @@ def print_header(): \\begin{small} \\begin{center} \\begin{tabular}{rccccccccccl} - & -\\hspace*{0.6in} & -\\hspace*{0.3in} & -\\hspace*{0.1in} & -\\hspace*{0.1in} & -\\hspace*{0.2in} & -\\hspace*{0.2in} & -\\hspace*{0.1in} & -\\hspace*{0.3in} & -\\hspace*{0.3in} & -\\hspace*{0.3in} \\\\ & \\instbitrange{31}{27} & \\instbitrange{26}{22} & @@ -363,8 +350,8 @@ def print_header(): \\cline{2-11} & \\multicolumn{1}{|c|}{rd} & -\\multicolumn{8}{c|}{LUI-immediate} & -\\multicolumn{1}{c|}{opcode} & LUI-type \\\\ +\\multicolumn{8}{c|}{upper immediate} & +\\multicolumn{1}{c|}{opcode} & U-type \\\\ \\cline{2-11} & \\multicolumn{1}{|c|}{rd} & @@ -418,296 +405,106 @@ def print_footer(caption): \\end{table} """ % (caption and '\\caption{Instruction listing for RISC-V}' or '') -def print_insts(opcode,name,type,min,max): - for n in namelist: - if yank(match[n],opcode_base,opcode_size) == opcode or n == name: - if type == -1 or types[n] == type: - if types[n] == 0: - print_unimp_type(n,match[n],arguments[n]) - elif types[n] == 1: - print_j_type(n,match[n],arguments[n]) - elif types[n] == 2: - print_lui_type(n,match[n],arguments[n]) - elif types[n] == 3: - print_i_type(n,match[n],arguments[n]) - elif types[n] == 4 \ - and (min == -1 or yank(match[n],5,10) >= min) \ - and (max == -1 or yank(match[n],5,10) <= max): - print_r_type(n,match[n],arguments[n]) - elif types[n] == 5: - print_r4_type(n,match[n],arguments[n]) - elif types[n] == 6: - print_ish_type(n,match[n],arguments[n]) - elif types[n] == 7: - print_ishw_type(n,match[n],arguments[n]) - elif types[n] == 8: - print_r4_rm_type(n,match[n],arguments[n]) - elif types[n] == 9: - print_r_rm_type(n,match[n],arguments[n]) - elif types[n] == 10: - print_b_type(n,match[n],arguments[n]) +def print_inst(n): + if 'shamt' in arguments[n]: + print_ish_type(n, match[n], arguments[n]) + elif 'shamtw' in arguments[n]: + print_ishw_type(n, match[n], arguments[n]) + elif 'imm25' in arguments[n]: + print_j_type(n, match[n], arguments[n]) + elif 'imm20' in arguments[n]: + print_lui_type(n, match[n], arguments[n]) + elif 'imm12' in arguments[n]: + print_i_type(n, match[n], arguments[n]) + elif 'imm12hi' in arguments[n]: + print_b_type(n, match[n], arguments[n]) + elif 'rs3' in arguments[n] and 'rm' in arguments[n]: + print_r4_rm_type(n, match[n], arguments[n]) + elif 'rs3' in arguments[n]: + print_r4_type(n, match[n], arguments[n]) + elif 'rm' in arguments[n]: + print_r_rm_type(n, match[n], arguments[n]) + else: + print_r_type(n, match[n], arguments[n]) -def make_latex_table(): - print_header() - print_subtitle('Unimplemented Instruction') - print_insts(0x00,'',-1,-1,-1) - print_subtitle('Control Transfer Instructions') - print_insts(0x67,'',-1,-1,-1) - print_insts(0x6f,'',-1,-1,-1) - print_insts(0x63,'',-1,-1,-1) - print_insts(0x6b,'',-1,-1,-1) - print_subtitle('Memory Instructions') - print_insts(0x03,'',-1,-1,-1) - print_insts(0x23,'',-1,-1,-1) - print_subtitle('Atomic Memory Instructions') - print_insts(0x2b,'',-1,-1,-1) - print_footer(0) +def print_insts(*names): + for n in names: + print_inst(n) +def make_latex_table(): print_header() - print_subtitle('Integer Compute Instructions') - print_insts(0x13,'',-1,-1,-1) - print_insts(0x33,'',-1,-1,-1) - print_insts(0x37,'',-1,-1,-1) - print_subtitle('32-bit Integer Compute Instructions') - print_insts(0x1b,'',-1,-1,-1) - print_insts(0x3b,'',-1,-1,-1) + print_subtitle('RV32I Instruction Subset') + print_insts('lui', 'auipc') + print_insts('j', 'jal', 'jalr', 'beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu') + print_insts('lb', 'lh', 'lw', 'lbu', 'lhu', 'sb', 'sh', 'sw') + print_insts('addi', 'slli', 'slti', 'sltiu', 'xori', 'srli', 'srai', 'ori', 'andi') + print_insts('add', 'sub', 'sll', 'slt', 'sltu', 'xor', 'srl', 'sra', 'or', 'and') + print_insts('fence.i', 'fence') + print_insts('syscall', 'break', 'rdcycle', 'rdtime', 'rdinstret') print_footer(0) print_header() - print_subtitle('Floating-Point Memory Instructions') - print_insts(0x07,'',-1,-1,-1) - print_insts(0x27,'',-1,-1,-1) - print_subtitle('Floating-Point Compute Instructions') - print_insts(-1,'fadd.s',-1,-1,-1) - print_insts(-1,'fsub.s',-1,-1,-1) - print_insts(-1,'fmul.s',-1,-1,-1) - print_insts(-1,'fdiv.s',-1,-1,-1) - print_insts(-1,'fsqrt.s',-1,-1,-1) - print_insts(-1,'fmin.s',-1,-1,-1) - print_insts(-1,'fmax.s',-1,-1,-1) - print_insts(-1,'fadd.d',-1,-1,-1) - print_insts(-1,'fsub.d',-1,-1,-1) - print_insts(-1,'fmul.d',-1,-1,-1) - print_insts(-1,'fdiv.d',-1,-1,-1) - print_insts(-1,'fsqrt.d',-1,-1,-1) - print_insts(-1,'fmin.d',-1,-1,-1) - print_insts(-1,'fmax.d',-1,-1,-1) - print_insts(-1,'fmadd.s',-1,-1,-1) - print_insts(-1,'fmsub.s',-1,-1,-1) - print_insts(-1,'fnmsub.s',-1,-1,-1) - print_insts(-1,'fnmadd.s',-1,-1,-1) - print_insts(-1,'fmadd.d',-1,-1,-1) - print_insts(-1,'fmsub.d',-1,-1,-1) - print_insts(-1,'fnmsub.d',-1,-1,-1) - print_insts(-1,'fnmadd.d',-1,-1,-1) + print_subtitle('RV64I Instruction Subset') + print_insts('lwu', 'ld', 'sd') + print_insts('addiw', 'slliw', 'srliw', 'sraiw') + print_insts('addw', 'subw', 'sllw', 'srlw', 'sraw') + print_subtitle('RV32M Instruction Subset') + print_insts('mul', 'mulh', 'mulhsu', 'mulhu') + print_insts('div', 'divu', 'rem', 'remu') + print_subtitle('RV64M Instruction Subset') + print_insts('mulw', 'divw', 'divuw', 'remw', 'remuw') + print_subtitle('RV32A Instruction Subset') + print_insts('amoadd.w', 'amoswap.w', 'amoand.w', 'amoor.w') + print_insts('amomin.w', 'amomax.w', 'amominu.w', 'amomaxu.w') + print_insts('lr.w', 'sc.w') print_footer(0) print_header() - print_subtitle('Floating-Point Move \& Conversion Instructions') - print_insts(-1,'fsgnj.s',-1,-1,-1) - print_insts(-1,'fsgnjn.s',-1,-1,-1) - print_insts(-1,'fsgnjx.s',-1,-1,-1) - print_insts(-1,'fsgnj.d',-1,-1,-1) - print_insts(-1,'fsgnjn.d',-1,-1,-1) - print_insts(-1,'fsgnjx.d',-1,-1,-1) - print_insts(-1,'fcvt.s.d',-1,-1,-1) - print_insts(-1,'fcvt.d.s',-1,-1,-1) - print_subtitle('Integer to Floating-Point Move \& Conversion Instructions') - print_insts(-1,'fcvt.s.l',-1,-1,-1) - print_insts(-1,'fcvt.s.lu',-1,-1,-1) - print_insts(-1,'fcvt.s.w',-1,-1,-1) - print_insts(-1,'fcvt.s.wu',-1,-1,-1) - print_insts(-1,'fcvt.d.l',-1,-1,-1) - print_insts(-1,'fcvt.d.lu',-1,-1,-1) - print_insts(-1,'fcvt.d.w',-1,-1,-1) - print_insts(-1,'fcvt.d.wu',-1,-1,-1) - print_insts(-1,'mxtf.s',-1,-1,-1) - print_insts(-1,'mxtf.d',-1,-1,-1) - print_insts(-1,'mtfsr',-1,-1,-1) - print_subtitle('Floating-Point to Integer Move \& Conversion Instructions') - print_insts(-1,'fcvt.l.s',-1,-1,-1) - print_insts(-1,'fcvt.lu.s',-1,-1,-1) - print_insts(-1,'fcvt.w.s',-1,-1,-1) - print_insts(-1,'fcvt.wu.s',-1,-1,-1) - print_insts(-1,'fcvt.l.d',-1,-1,-1) - print_insts(-1,'fcvt.lu.d',-1,-1,-1) - print_insts(-1,'fcvt.w.d',-1,-1,-1) - print_insts(-1,'fcvt.wu.d',-1,-1,-1) - print_insts(-1,'mftx.s',-1,-1,-1) - print_insts(-1,'mftx.d',-1,-1,-1) - print_insts(-1,'mffsr',-1,-1,-1) + print_subtitle('RV64A Instruction Subset') + print_insts('amoadd.d', 'amoswap.d', 'amoand.d', 'amoor.d') + print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d') + print_insts('lr.d', 'sc.d') + print_subtitle('RV32F Instruction Subset') + print_insts('flw', 'fsw') + print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s', 'fmin.s', 'fmax.s') + print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s') + print_insts('fsgnj.s', 'fsgnjn.s', 'fsgnjx.s') + print_insts('fcvt.s.w', 'fcvt.s.wu', 'mxtf.s', 'mtfsr') + print_insts('fcvt.w.s', 'fcvt.wu.s', 'mftx.s', 'mffsr') + print_insts('feq.s', 'flt.s', 'fle.s') print_footer(0) print_header() - print_subtitle('Floating-Point Compare Instructions') - print_insts(-1,'feq.s',-1,-1,-1) - print_insts(-1,'flt.s',-1,-1,-1) - print_insts(-1,'fle.s',-1,-1,-1) - print_insts(-1,'feq.d',-1,-1,-1) - print_insts(-1,'flt.d',-1,-1,-1) - print_insts(-1,'fle.d',-1,-1,-1) - print_subtitle('Miscellaneous Memory Instructions') - print_insts(0x2f,'',-1,-1,-1) - print_subtitle('System Instructions') - print_insts(0x77,'',-1,-1,-1) + print_subtitle('RV64F Instruction Subset') + print_insts('fcvt.s.l', 'fcvt.s.lu') + print_insts('fcvt.l.s', 'fcvt.lu.s') + print_subtitle('RV32D Instruction Subset') + print_insts('fld', 'fsd') + print_insts('fadd.d', 'fsub.d', 'fmul.d', 'fdiv.d', 'fsqrt.d', 'fmin.d', 'fmax.d') + print_insts('fmadd.d', 'fmsub.d', 'fnmsub.d', 'fnmadd.d') + print_insts('fsgnj.d', 'fsgnjn.d', 'fsgnjx.d') + print_insts('fcvt.d.w', 'fcvt.d.wu') + print_insts('fcvt.w.d', 'fcvt.wu.d') + print_insts('feq.d', 'flt.d', 'fle.d') + print_subtitle('RV64D Instruction Subset') + print_insts('fcvt.d.l', 'fcvt.d.lu', 'mxtf.d') + print_insts('fcvt.l.d', 'fcvt.lu.d', 'mftx.d') + print_insts('fcvt.s.d', 'fcvt.d.s') print_footer(1) -def str_verilog_arg(arg0,arg1,match,arguments): - if arg0 in arguments: - return '?' * (arglut[arg0][0] - arglut[arg0][1] + 1) - elif arg1 in arguments: - return '?' * (arglut[arg0][0] - arglut[arg0][1] + 1) - else: - start = arglut[arg0][1] - len = arglut[arg0][0] - arglut[arg0][1] + 1 - return binary(yank(match,start,len),len) - -def print_verilog_unimp_type(name,match,arguments): - print "`define %-10s 32'b%s" % \ - ( \ - name.replace('.','_').upper(), \ - '0'*32 \ - ) - -def print_verilog_j_type(name,match,arguments): - print "`define %-10s 32'b%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('imm25','',match,arguments), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_lui_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('imm20','',match,arguments), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_b_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('imm12hi','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ - str_verilog_arg('imm12lo','',match,arguments), \ - binary(yank(match,7,3),3), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_i_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('imm12','',match,arguments), \ - binary(yank(match,7,3),3), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_ish_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,16,6),6), \ - str_verilog_arg('shamt','',match,arguments), \ - binary(yank(match,7,3),3), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_ishw_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_0_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - binary(yank(match,16,6),6), \ - str_verilog_arg('shamtw','',match,arguments), \ - binary(yank(match,7,3),3), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_r4_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ - str_verilog_arg('rs3','',match,arguments), \ - binary(yank(match,9,3),3), \ - binary(yank(match,7,2),2), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_r4_rm_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ - str_verilog_arg('rs3','',match,arguments), \ - str_verilog_arg('rm','',match,arguments), \ - binary(yank(match,7,2),2), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_r_rm_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ - binary(yank(match,12,5),5), \ - str_verilog_arg('rm','',match,arguments), \ - binary(yank(match,7,2),2), \ - binary(yank(match,0,7),7) \ - ) - -def print_verilog_r_type(name,match,arguments): - print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ - ( \ - name.replace('.','_').upper(), \ - str_verilog_arg('rd','',match,arguments), \ - str_verilog_arg('rs1','',match,arguments), \ - str_verilog_arg('rs2','',match,arguments), \ - binary(yank(match,7,10),10), \ - binary(yank(match,0,7),7) \ - ) +def print_verilog_insn(name): + s = "`define %-10s 32'b" % name.replace('.', '_').upper() + for i in range(31, -1, -1): + if yank(mask[name], i, 1): + s = '%s%d' % (s, yank(match[name], i, 1)) + else: + s = s + '?' + print s def make_verilog(): print '/* Automatically generated by parse-opcodes */' for name in namelist: - if types[name] == 0: - print_verilog_unimp_type(name,match[name],arguments[name]) - elif types[name] == 1: - print_verilog_j_type(name,match[name],arguments[name]) - elif types[name] == 2: - print_verilog_lui_type(name,match[name],arguments[name]) - elif types[name] == 3: - print_verilog_i_type(name,match[name],arguments[name]) - elif types[name] == 4: - print_verilog_r_type(name,match[name],arguments[name]) - elif types[name] == 5: - print_verilog_r4_type(name,match[name],arguments[name]) - elif types[name] == 6: - print_verilog_ish_type(name,match[name],arguments[name]) - elif types[name] == 7: - print_verilog_ishw_type(name,match[name],arguments[name]) - elif types[name] == 8: - print_verilog_r4_rm_type(name,match[name],arguments[name]) - elif types[name] == 9: - print_verilog_r_rm_type(name,match[name],arguments[name]) - elif types[name] == 10: - print_verilog_b_type(name,match[name],arguments[name]) + print_verilog_insn(name) for line in sys.stdin: line = line.partition('#') @@ -762,22 +559,6 @@ for line in sys.stdin: mask[name] = mymask match[name] = mymatch - types[name] = typelut[yank(mymatch,0,7)] - if 'shamtw' in arguments[name]: - types[name] = 7 - elif 'imm12' in arguments[name]: - types[name] = 3 - elif 'shamt' in arguments[name]: - types[name] = 6 - elif types[name] == 4 and 'rs3' in arguments[name]: - types[name] = 5 - elif types[name] == 5 and 'rm' in arguments[name]: - types[name] = 8 - elif types[name] == 4 and 'rm' in arguments[name]: - types[name] = 9 - elif name == 'vsetvl': - types[name] = 3 - namelist.append(name) if sys.argv[1] == '-tex': |