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-rw-r--r--opcodes-rvv9
1 files changed, 7 insertions, 2 deletions
diff --git a/opcodes-rvv b/opcodes-rvv
index 33a7ae6..042e84a 100644
--- a/opcodes-rvv
+++ b/opcodes-rvv
@@ -12,10 +12,10 @@ vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57
vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57
#
-# Vector Loads and Store (including segment part)
+# Vector Loads and Store
# https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc
#
-# Vector Unit-Stride Instructions
+# Vector Unit-Stride Instructions (including segment part)
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions
vlb.v nf 28..26=4 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07
vlh.v nf 28..26=4 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07
@@ -72,6 +72,11 @@ vlbuff.v nf 28..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07
vlhuff.v nf 28..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07
vlwuff.v nf 28..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07
+# Vector Load/Store Whole Registers
+# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions
+vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07
+vs1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vs3 6..0=0x27
+
# Vector Floating-Point Instructions
# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions
# OPFVF