move opcode of zvb* (#236)

* move opcode of zvbb

* move all zvk* out

9 files changed, 0 insertions, 179 deletions

diff --git a/unratified/rv_zvbb b/unratified/rv_zvbb
deleted file mode 100644
index dc48ee2..0000000
--- a/unratified/rv_zvbb
+++ /dev/null
@@ -1,37 +0,0 @@
-# Zvbb - Vector Bit-manipulation used in Cryptography
-
-# Vector And-Not
-vandn.vv     31..26=0x01 vm vs2 vs1 14..12=0x0 vd 6..0=0x57
-vandn.vx     31..26=0x01 vm vs2 rs1 14..12=0x4 vd 6..0=0x57
-
-# Vector Reverse Bits in Elements
-vbrev.v      31..26=0x12 vm vs2 19..15=0xA 14..12=0x2 vd 6..0=0x57
-
-# Vector Reverse Bits in Bytes
-vbrev8.v     31..26=0x12 vm vs2 19..15=0x8 14..12=0x2 vd 6..0=0x57
-
-# Vector Reverse Bytes
-vrev8.v      31..26=0x12 vm vs2 19..15=0x9 14..12=0x2 vd 6..0=0x57
-
-# Vector Count Leading Zeros
-vclz.v       31..26=0x12 vm vs2 19..15=0xC 14..12=0x2 vd 6..0=0x57
-
-# Vector Count Trailing Zeros
-vctz.v       31..26=0x12 vm vs2 19..15=0xD 14..12=0x2 vd 6..0=0x57
-
-# Vector Population Count
-vcpop.v       31..26=0x12 vm vs2 19..15=0xE 14..12=0x2 vd 6..0=0x57
-
-# Vector Rotate Left
-vrol.vv      31..26=0x15         vm vs2 vs1     14..12=0x0 vd 6..0=0x57
-vrol.vx      31..26=0x15         vm vs2 rs1     14..12=0x4 vd 6..0=0x57
-
-# Vector Rotate Right
-vror.vv      31..26=0x14         vm vs2 vs1     14..12=0x0 vd 6..0=0x57
-vror.vx      31..26=0x14         vm vs2 rs1     14..12=0x4 vd 6..0=0x57
-vror.vi      31..27=0xa  zimm6hi vm vs2 zimm6lo 14..12=0x3 vd 6..0=0x57
-
-# Vector Widening Shift Left Logical
-vwsll.vv     31..26=0x35 vm vs2 vs1   14..12=0x0 vd 6..0=0x57
-vwsll.vx     31..26=0x35 vm vs2 rs1   14..12=0x4 vd 6..0=0x57
-vwsll.vi     31..26=0x35 vm vs2 zimm5 14..12=0x3 vd 6..0=0x57
diff --git a/unratified/rv_zvkg b/unratified/rv_zvkg
deleted file mode 100644
index ed7bf32..0000000
--- a/unratified/rv_zvkg
+++ /dev/null
@@ -1,8 +0,0 @@
-# Zvkg - Vector GCM/GMAC
-
-# Vector Multiply over GHASH Galois-Field
-vgmul.vv 31..26=0x28 25=1 vs2 19..15=0x11 14..12=0x2 vd 6..0=0x77
-
-# Vector Add-Multiply over GHASH Galois-Field
-vghsh.vv 31..26=0x2C 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77
-
diff --git a/unratified/rv_zvkn b/unratified/rv_zvkn
deleted file mode 100644
index 5a17e6d..0000000
--- a/unratified/rv_zvkn
+++ /dev/null
@@ -1,46 +0,0 @@
-# Zvkn, Vector Crypto Extension, NIST Algorithm Suite
-
-# Import Zvbb
-$import rv_zvbb::vandn.vv
-$import rv_zvbb::vandn.vx
-$import rv_zvbb::vbrev.v
-$import rv_zvbb::vbrev8.v
-$import rv_zvbb::vrev8.v
-$import rv_zvbb::vrol.vv
-$import rv_zvbb::vrol.vx
-$import rv_zvbb::vror.vv
-$import rv_zvbb::vror.vx
-$import rv_zvbb::vror.vi
-$import rv_zvbb::vclz.v
-$import rv_zvbb::vctz.v
-$import rv_zvbb::vcpop.v
-$import rv_zvbb::vwsll.vv
-$import rv_zvbb::vwsll.vx
-$import rv_zvbb::vwsll.vi
-
-# Import Zvbc
-$import rv_zvbc::vclmul.vv
-$import rv_zvbc::vclmul.vx
-$import rv_zvbc::vclmulh.vv
-$import rv_zvbc::vclmulh.vx
-
-# Import Zvkned
-$import rv_zvkned::vaesef.vs
-$import rv_zvkned::vaesef.vv
-$import rv_zvkned::vaesem.vs
-$import rv_zvkned::vaesem.vv
-$import rv_zvkned::vaesdf.vs
-$import rv_zvkned::vaesdf.vv
-$import rv_zvkned::vaesdm.vs
-$import rv_zvkned::vaesdm.vv
-$import rv_zvkned::vaeskf1.vi
-$import rv_zvkned::vaeskf2.vi
-$import rv_zvkned::vaesz.vs
-
-# Import Zvknh.
-# "Zvkn" implies "Zvknhb". We import the instructions from 'rv_zvknha',
-# because we cannot import already imported instructions, 'rv_zvknhb'
-# imports them from 'rv_zvknha', and the instructions are identical.
-$import rv_zvknha::vsha2ms.vv
-$import rv_zvknha::vsha2ch.vv
-$import rv_zvknha::vsha2cl.vv
diff --git a/unratified/rv_zvkned b/unratified/rv_zvkned
deleted file mode 100644
index 572b465..0000000
--- a/unratified/rv_zvkned
+++ /dev/null
@@ -1,21 +0,0 @@
-# Zvkned - Vector Crypto AES Encryption & Decryption (Singe Round)
-
-# AES Single Round Decryption
-vaesdf.vv    31..26=0x28 25=1 vs2 19..15=0x1 14..12=0x2 vd 6..0=0x77
-vaesdf.vs    31..26=0x29 25=1 vs2 19..15=0x1 14..12=0x2 vd 6..0=0x77
-vaesdm.vv    31..26=0x28 25=1 vs2 19..15=0x0 14..12=0x2 vd 6..0=0x77
-vaesdm.vs    31..26=0x29 25=1 vs2 19..15=0x0 14..12=0x2 vd 6..0=0x77
-
-# AES Single Round Encryption
-vaesef.vv    31..26=0x28 25=1 vs2 19..15=0x3 14..12=0x2 vd 6..0=0x77
-vaesef.vs    31..26=0x29 25=1 vs2 19..15=0x3 14..12=0x2 vd 6..0=0x77
-vaesem.vv    31..26=0x28 25=1 vs2 19..15=0x2 14..12=0x2 vd 6..0=0x77
-vaesem.vs    31..26=0x29 25=1 vs2 19..15=0x2 14..12=0x2 vd 6..0=0x77
-
-# AES Scalar Round Zero Encryption/Decryption
-vaesz.vs     31..26=0x29 25=1 vs2 19..15=0x7 14..12=0x2 vd 6..0=0x77
-
-# AES-128 Forward Key Schedule
-vaeskf1.vi   31..26=0x22 25=1 vs2 zimm5      14..12=0x2 vd 6..0=0x77
-# AES-256 Forward Key Schedule
-vaeskf2.vi   31..26=0x2A 25=1 vs2 zimm5      14..12=0x2 vd 6..0=0x77
diff --git a/unratified/rv_zvknha b/unratified/rv_zvknha
deleted file mode 100644
index a09a36c..0000000
--- a/unratified/rv_zvknha
+++ /dev/null
@@ -1,9 +0,0 @@
-# Zvknha - Vector Crypto SHA-256 Secure Hash
-#
-# The following 3 instructions are defined in both Zvknha and Zvknhb:
-#  - in Zvknha, they support SHA-256 (SEW=32) only,
-#  - in Zvknhb, they support both SHA-256 (SEW=32) and SHA-512 (SEW=64).
-
-vsha2ms.vv    31..26=0x2D 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77
-vsha2ch.vv    31..26=0x2E 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77
-vsha2cl.vv    31..26=0x2F 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77
diff --git a/unratified/rv_zvknhb b/unratified/rv_zvknhb
deleted file mode 100644
index c0b0d8f..0000000
--- a/unratified/rv_zvknhb
+++ /dev/null
@@ -1,9 +0,0 @@
-# Zvknhb - Vector Crypto SHA-256 and SHA-512 Secure Hash
-#
-# The following 3 instructions are defined in both Zvknha and Zvknhb:
-#  - in Zvknha, they support SHA-256 (SEW=32) only,
-#  - in Zvknhb, they support both SHA-256 (SEW=32) and SHA-512 (SEW=64).
-
-$import rv_zvknha::vsha2ms.vv
-$import rv_zvknha::vsha2ch.vv
-$import rv_zvknha::vsha2cl.vv
diff --git a/unratified/rv_zvks b/unratified/rv_zvks
deleted file mode 100644
index b5448bf..0000000
--- a/unratified/rv_zvks
+++ /dev/null
@@ -1,34 +0,0 @@
-# Zvk, Vector Crypto Extension, ShangMi Algorithm Suite
-
-# Import Zvbb
-$import rv_zvbb::vandn.vv
-$import rv_zvbb::vandn.vx
-$import rv_zvbb::vbrev.v
-$import rv_zvbb::vbrev8.v
-$import rv_zvbb::vrev8.v
-$import rv_zvbb::vrol.vv
-$import rv_zvbb::vrol.vx
-$import rv_zvbb::vror.vv
-$import rv_zvbb::vror.vx
-$import rv_zvbb::vror.vi
-$import rv_zvbb::vclz.v
-$import rv_zvbb::vctz.v
-$import rv_zvbb::vcpop.v
-$import rv_zvbb::vwsll.vv
-$import rv_zvbb::vwsll.vx
-$import rv_zvbb::vwsll.vi
-
-# Import Zvbc
-$import rv_zvbc::vclmul.vv
-$import rv_zvbc::vclmul.vx
-$import rv_zvbc::vclmulh.vv
-$import rv_zvbc::vclmulh.vx
-
-# Import Zvksed
-$import rv_zvksed::vsm4k.vi
-$import rv_zvksed::vsm4r.vv
-$import rv_zvksed::vsm4r.vs
-
-# Import Zvksh
-$import rv_zvksh::vsm3c.vi
-$import rv_zvksh::vsm3me.vv
diff --git a/unratified/rv_zvksed b/unratified/rv_zvksed
deleted file mode 100644
index b0b3037..0000000
--- a/unratified/rv_zvksed
+++ /dev/null
@@ -1,8 +0,0 @@
-# Zvksed - Vector Crypto SM4 (Block Cipher)
-
-# SM4 Key Expansion
-vsm4k.vi     31..26=0x21 25=1 vs2 zimm5       14..12=0x2 vd 6..0=0x77
-
-# SM4 Encryption/Decryption Rounds
-vsm4r.vv     31..26=0x28 25=1 vs2 19..15=0x10 14..12=0x2 vd 6..0=0x77
-vsm4r.vs     31..26=0x29 25=1 vs2 19..15=0x10 14..12=0x2 vd 6..0=0x77
diff --git a/unratified/rv_zvksh b/unratified/rv_zvksh
deleted file mode 100644
index 2dc6f6c..0000000
--- a/unratified/rv_zvksh
+++ /dev/null
@@ -1,7 +0,0 @@
-# Zvksh - Vector Crypto SM3 (Hash)
-
-# SM3 Message Compression
-vsm3c.vi     31..26=0x2B 25=1 vs2 zimm5 14..12=0x2 vd 6..0=0x77
-
-# SM3 Message Expansion
-vsm3me.vv    31..26=0x20 25=1 vs2 vs1   14..12=0x2 vd 6..0=0x77