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| author | Eric Gouriou <ego@rivosinc.com> | 2023-05-01 21:57:16 -0700 |
|---|---|---|
| committer | Eric Gouriou <ego@rivosinc.com> | 2023-05-01 21:57:16 -0700 |
| commit | 199e646f2a8e36533c92280a5fba0d259ba7fbfb (patch) | |
| tree | cb37a856a49ecb27592a0e6e2d8f23155627436e /unratified/rv64_zpn | |
| parent | bb64568616b364e7103910f5dd363bc9cad1bb0a (diff) | |
| download | riscv-opcodes-199e646f2a8e36533c92280a5fba0d259ba7fbfb.zip riscv-opcodes-199e646f2a8e36533c92280a5fba0d259ba7fbfb.tar.gz riscv-opcodes-199e646f2a8e36533c92280a5fba0d259ba7fbfb.tar.bz2 | |
Support for Zvk, Vector Cryptography Extensions
Add encodings for all instructions in the Zvk extensions:
- Zvbb, Vector Bit-manipulation instructions used in Cryptography,
- Zvbc, Vector Carryless Multiplication
- Zvkg, Vector GCM/GMAC instruction for Cryptography,
- Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single
Round),
- Zvknha, Zvknhb, NIST Suite: Vector SHA-2,
- Zvksed, ShangMi Suite: SM4 Block Cipher Instructions
- Zvkssh, ShangMi Suite: SM3 Hash Function Instructions
Add two "shorthand" extensions:
- Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh
- Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh
Three new fields are listed in constants.py:
- 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh),
and 5-bit shift constant (vwsll.vi in Zvbb)
- 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount
in vror.vi.
The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the
P opcode space. Some encodings conflict with proposed instructions
in the P extension (packed SIMD). Zvk and P are exclusive of each
other, no implementation will implement both. Conflicting P instructions
are marked as pseudo of the Zvk instructions.
The encodings match the current documentation of the specification
at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>,
at Version v0.9.1, 25 April, 2023 (Freeze Candidate).
Co-authored-by: Eric Gouriou <ego@rivosinc.com>
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Co-authored-by: Kornel Duleba <mindal@semihalf.com>
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
Diffstat (limited to 'unratified/rv64_zpn')
| -rw-r--r-- | unratified/rv64_zpn | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/unratified/rv64_zpn b/unratified/rv64_zpn index c90bf1e..fa484fa 100644 --- a/unratified/rv64_zpn +++ b/unratified/rv64_zpn @@ -27,7 +27,7 @@ urstas32 31..25=0b1101000 rs2 rs1 14..12=0b010 rd 6..0=0b1 kstas32 31..25=0b1100000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 ukstas32 31..25=0b1110000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 stsa32 31..25=0b1111001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -rstsa32 31..25=0b1011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +$pseudo_op rv_zvkg::vghsh.vv rstsa32 31..25=0b1011001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 urstsa32 31..25=0b1101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 kstsa32 31..25=0b1100001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 ukstsa32 31..25=0b1110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 @@ -40,7 +40,7 @@ srai32.u 31..25=0b1000000 imm5 rs1 14..12=0b010 rd 6..0=0b1 srl32 31..25=0b0101001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 srli32 31..25=0b0111001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 srl32.u 31..25=0b0110001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -srli32.u 31..25=0b1000001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 +$pseudo_op rv_zvksh::vsm3me.vv srli32.u 31..25=0b1000001 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 sll32 31..25=0b0101010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 slli32 31..25=0b0111010 imm5 rs1 14..12=0b010 rd 6..0=0b1110111 ksll32 31..25=0b0110010 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 @@ -50,7 +50,7 @@ kslra32.u 31..25=0b0110011 rs2 rs1 14..12=0b010 rd 6..0=0b1 smin32 31..25=0b1001000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 umin32 31..25=0b1010000 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 smax32 31..25=0b1001001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 -umax32 31..25=0b1010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 +$pseudo_op rv_zvkned::vaesdf.vv umax32 31..25=0b1010001 rs2 rs1 14..12=0b010 rd 6..0=0b1110111 khmbb16 31..25=0b1101110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 khmbt16 31..25=0b1110110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 khmtt16 31..25=0b1111110 rs2 rs1 14..12=0b001 rd 6..0=0b1110111 |