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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-14 23:19:39 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-31 10:07:27 -0700 |
| commit | 7231f5a8582019ca5eb0037ba05ceed8c44f35a8 (patch) | |
| tree | 973b77c507e337b43cfb71e056265de02c10b742 /parse_opcodes | |
| parent | 75f44b5b949922813b7ab971d5ececf863592b0a (diff) | |
| download | riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.zip riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.tar.gz riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.tar.bz2 | |
hyperviosr: add csr mask and interrupt macro name
This part copy the implementation which has been merged in spike
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'parse_opcodes')
| -rwxr-xr-x | parse_opcodes | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/parse_opcodes b/parse_opcodes index 4fd7489..56833be 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -60,11 +60,15 @@ causes = [ (0x07, 'store access'), (0x08, 'user_ecall'), (0x09, 'supervisor_ecall'), - (0x0A, 'hypervisor_ecall'), + (0x0A, 'virtual_supervisor_ecall'), (0x0B, 'machine_ecall'), (0x0C, 'fetch page fault'), (0x0D, 'load page fault'), (0x0F, 'store page fault'), + (0x14, 'fetch guest page fault'), + (0x15, 'load guest page fault'), + (0x16, 'virtual instruction'), + (0x17, 'store guest page fault'), ] csrs = [ |