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| author | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-26 13:15:00 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@rivosinc.com> | 2023-01-26 13:15:00 -0800 |
| commit | ebd4dbf85b0251d5a25680bc1a451b6f613ecb9d (patch) | |
| tree | 6ee8f53ce4c2a56b09af7076e99edece174f70b0 /parse.py | |
| parent | b9c3ee2d65f6f06319829bdcc15e18c9bdb7975e (diff) | |
| download | riscv-opcodes-ebd4dbf85b0251d5a25680bc1a451b6f613ecb9d.zip riscv-opcodes-ebd4dbf85b0251d5a25680bc1a451b6f613ecb9d.tar.gz riscv-opcodes-ebd4dbf85b0251d5a25680bc1a451b6f613ecb9d.tar.bz2 | |
Add support for Svadu
The Svadu extension (https://github.com/riscv/riscv-svadu) adds the
HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the
A/D bits in the PTE. Provide the bit encodings for the HADE support.
Diffstat (limited to 'parse.py')
0 files changed, 0 insertions, 0 deletions