Support for Zvk, Vector Cryptography Extensions

Add encodings for all instructions in the Zvk extensions:
 - Zvbb, Vector Bit-manipulation instructions used in Cryptography,
 - Zvbc, Vector Carryless Multiplication
 - Zvkg, Vector GCM/GMAC instruction for Cryptography,
 - Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single
   Round),
 - Zvknha, Zvknhb, NIST Suite: Vector SHA-2,
 - Zvksed, ShangMi Suite: SM4 Block Cipher Instructions
 - Zvkssh, ShangMi Suite: SM3 Hash Function Instructions

Add two "shorthand" extensions:
 - Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh
 - Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh

Three new fields are listed in constants.py:
 - 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh),
   and 5-bit shift constant (vwsll.vi in Zvbb)
 - 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount
   in vror.vi.

The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the
P opcode space. Some encodings conflict with proposed instructions
in the P extension (packed SIMD). Zvk and P are exclusive of each
other, no implementation will implement both. Conflicting P instructions
are marked as pseudo of the Zvk instructions.

The encodings match the current documentation of the specification
at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>,
at Version v0.9.1, 25 April, 2023 (Freeze Candidate).

Co-authored-by: Eric Gouriou <ego@rivosinc.com>
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Co-authored-by: Kornel Duleba <mindal@semihalf.com>
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>

1 files changed, 1 insertions, 4 deletions

diff --git a/parse.py b/parse.py
index 47846b7..e78a158 100755
--- a/parse.py
+++ b/parse.py
@@ -958,10 +958,7 @@ if __name__ == "__main__":
 
     if '-c' in sys.argv[1:]:
         instr_dict_c = create_inst_dict(extensions, False, 
-                include_pseudo_ops=['pause', 'prefetch_r', 'prefetch_w', 'prefetch_i',
-                                    'slli_rv32', 'srli_rv32', 'srai_rv32',
-                                    'slli_rv128', 'srli_rv128', 'srai_rv128',
-                                    ])
+                                        include_pseudo_ops=emitted_pseudo_ops)
         instr_dict_c = collections.OrderedDict(sorted(instr_dict_c.items()))
         make_c(instr_dict_c)
         logging.info('encoding.out.h generated successfully')