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author | Florian Zaruba <zarubaf@iis.ee.ethz.ch> | 2019-02-11 19:41:39 +0100 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2019-02-11 10:41:39 -0800 |
commit | a2f7cf2080b3809de1141b9652c3dce341053e2a (patch) | |
tree | 835b06a09d20b9bf0023c8c6723b3ac43e2abc4e /parse-opcodes | |
parent | ec25bc8728fcdc3e960213ff85773efd61673aa8 (diff) | |
download | riscv-opcodes-a2f7cf2080b3809de1141b9652c3dce341053e2a.zip riscv-opcodes-a2f7cf2080b3809de1141b9652c3dce341053e2a.tar.gz riscv-opcodes-a2f7cf2080b3809de1141b9652c3dce341053e2a.tar.bz2 |
Add SystemVerilog generation (#24)
Diffstat (limited to 'parse-opcodes')
-rwxr-xr-x | parse-opcodes | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/parse-opcodes b/parse-opcodes index a2c5322..73bbec8 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -889,6 +889,25 @@ def make_chisel(): print(' }') print('}') +def print_sverilog_insn(name): + s = " localparam [31:0] %-18s = 32'b" % name.replace('.', '_').upper() + for i in range(31, -1, -1): + if yank(mask[name], i, 1): + s = '%s%d' % (s, yank(match[name], i, 1)) + else: + s = s + '?' + print(s + ";") + +def make_sverilog(): + print('/* Automatically generated by parse-opcodes */') + print('package riscv_instr;') + for name in namelist: + print_sverilog_insn(name) + print(' /* CSR Addresses */') + for num, name in csrs+csrs32: + print(' localparam logic [11:0] CSR_%s = 12\'h%s;' % (name.upper(), hex(num)[2:])) + print('endpackage') + def signed(value, width): if 0 <= value < (1<<(width-1)): return value @@ -999,6 +1018,8 @@ elif sys.argv[1] == '-privtex': make_supervisor_latex_table() elif sys.argv[1] == '-chisel': make_chisel() +elif sys.argv[1] == '-sverilog': + make_sverilog() elif sys.argv[1] == '-c': make_c(match,mask) elif sys.argv[1] == '-go': |